37 results about "Single-ended signaling" patented technology

Using a transformation based at least in part on a non-simple orthogonal or unitary matrix, data may be transmitted over a data bus in a manner that is resilient to one or more types of signal noise, that does not require a common reference at the transmission and acquisition points, and/or that has a pin-efficiency that is greater than 50% and may approach that of single-ended signaling. Such transformations may be implemented in hardware in an efficient manner. Hybrid transformers that apply such transformations to selected subsets of signals to be transmitted may be used to adapt to various signal set sizes and/or transmission environment properties including noise and physical space requirements of given transmission environments.

Using a transformation based, at least in part, on a non-simple orthogonal matrix, data may be transmitted over a data bus in a manner that is resilient to one or more types of signal noise, that does not require a common reference at the transmission and acquisition points, and/or that has a pin-efficiency that is greater than 50% and may approach that of single-ended signaling. Such transformations may be implemented in hardware in an efficient manner. The transformation may be combined with methods from forward error correction to lower the required transmission power.

Aspects of a method and system for configurable differential or single-ended signaling in an integrated circuit. In this regard, a balun comprising one or more loops fabricated in a plurality of metal layers in an integrated circuit may enable conversion between unbalanced and balanced signals. In this regard, balanced signal output by a power amplifier may be converted to a balanced signal for transmission via an antenna. Similarly, an unbalanced signal received by an antenna may be converted to a balanced signal for amplification by an amplifier with a balanced input. The loops may be fabricated in transmission line media such as microstrip and/or stripline. The loops may comprise ferromagnetic material which may be deposited on and/or within the IC. Signals converted via the balun may be in the 61 GHz-61.5 GHz ISM band.

Design structures embodied in machine readable medium are provided. Embodiments of the design structures include a multimodal memory controller comprising: a transceiver circuit having at least one internal signal line, a first external signal line, a second external signal line, and a mode control signal line, the mode control signal line having asserted upon it a mode control signal, and the transceiver circuit configured to operate the external signal lines for single-ended signaling at a first voltage when the mode control signal is a first value and to operate the external signal lines for differential signaling at a second voltage when the mode control signal is a second value.

Techniques and mechanisms for configuring an integrated circuit (IC) chip to implement a protocol stack. In an embodiment, a transaction layer of the IC chip is operable to exchange with a link layer of the IC chip transaction layer packets (TLPs) having a format compatible with one defined in a Peripheral Component Interconnect Express™ (PCIe™) specification. Configuration circuitry of the IC chip provides for configuration of a first protocol stack including the transaction layer, circuitry of the link layer and a first physical layer of the IC chip. The configuration circuitry further provides for an alternative configuration of a second protocol stack including the transaction layer, circuitry of the link layer and a second physical layer of the IC chip. In another embodiment, the first protocol stack supports single-ended signaling to communicate TLP information, whereas the second protocol stack supports differential signaling to communicate TLP information.

A programmable differential signaling system includes a programmable bias generator and a plurality of input/output modules. The programmable bias generator is operably coupled to generate a first global bias signal and a second global signal based on desired signal properties of one of a plurality of differential signaling conventions. The a plurality of input/output modules is operably coupled to convert between differential signaling and single ended signaling, wherein actual signal properties of the differential signaling are regulated based on the first and second global bias signals to substantially equal the desired signal properties.

A multi-layer printed circuit board comprises: at least two insulation layers, respectively having glass fiber cloth and cured resin covering thereon, the insulation layers being stacked on each other; an internal trace layer formed between two neighboring insulation layers; and an external trace layer formed on an outer surface of the outermost insulation layer; wherein the insulation layers have a dielectric constant of 3.4 or less, and the internal and external trace layers have a trace width between 40 and 75 micrometers, such that the multi-layer printed circuit board has a characteristic impedance between 45 and 55 Ω in single-ended signaling and between 90 and 110 Ω in differential signaling.

A single-ended signaling system in which transmitted and returned signal currents are enabled to flow substantially parallel to one another and thereby maintain a substantially uniform impedance along the length of a single-ended signal conductor. A reference plane is disposed substantially parallel to a single-ended signaling conductor and coupled to the signaling conductor within a signal-receiving IC and to signaling supply voltage nodes within a signal-transmitting IC. By this arrangement, an signal current flowing to or from the receiving IC via the signaling conductor is conducted to the reference plane, thereby enabling a signal-return current to flow back to or back from the transmitting IC along a single path that is substantially parallel to the signal conductor.

A method of reducing crosstalk. The method may include forming a first contact over a first vertical conductor. The method may include forming a second contact over a second vertical conductor. The method may include forming a third contact over a third vertical conductor. The method may include forming a capacitive coupler between the first contact, the second contact, and the third contact, wherein the capacitive coupler is to cancel crosstalk received at the second vertical conductor and third vertical conductor from the first vertical conductor.

A scalable low voltage signaling (SLVS) serial interface structure is configured as a 0.4V NMOS totem-pole driver structure for both high speed differential signaling and slow speed single-ended signaling using the same 0.4V NMOS totem-pole driver structure. An un-terminated receiver (Rx) and a CMOS inverter comparator powered from a 0.4 volt supply, is used for receiving the slow speed single-ended 0-100 mega bits per second (Mbps) signaling in a data link. A terminated receiver (Rx) and a differential comparator powered from a 0.4 volt supply, is used for receiving the high speed differential 2 giga bits per second (Gbps) signaling in the data link.

A system of interconnected chips comprising a multi-chip module (MCM) includes a first processor chip, a second processor chip, and an MCM package configured to include the first processor chip, the second processor chip, and an interconnect circuit. The first processor chip is configured to include a first ground-referenced single-ended signaling (GRS) interface circuit. A first set of electrical traces fabricated within the MCM package and configured to couple the first GRS interface circuit to the interconnect circuit. The second processor chip is configured to include a second GRS interface circuit. A second set of electrical traces fabricated within the MCM package and configured to coupled the second GRS interface circuit to the interconnect circuit.

Mass-manufactured cables suitable for large communication centers may convert from differential PAM4 interface signaling to parallel single-ended NRZ transit signaling at 53.125 GBd to provide bidirectional data rates up to 800 Gbps and beyond. One illustrative cable embodiment includes: electrical conductors connected between a first connector and a second connector, each adapted to fit into an Ethernet port of a corresponding host device to receive an electrical input signal to the cable conveying an outbound data stream from the host device and to provide an electrical output signal from the cable conveying an inbound data stream to that host device. The electrical input and output signals employ differential PAM4 modulation to convey the inbound and outbound data streams. Each of the first and second connectors includes transceivers to perform clock and data recovery on the electrical input signal to extract and re-modulate the outbound data stream for transit via the electrical conductors as respective pairs of electrical transit signals employing single-ended NRZ modulation.

Systems, apparatuses, and methods for performing efficient data transfer in a computing system are disclosed. A computing system includes multiple transmitters sending singled-ended data signals to multiple receivers. A termination voltage is generated and sent to the multiple receivers. The termination voltage is coupled to each of signal termination circuitry and signal sampling circuitry within each of the multiple receivers. Any change in the termination voltage affects the termination circuitry and affects comparisons performed by the sampling circuitry. Received signals are reconstructed at the receivers using the received signals, the signal termination circuitry and the signal sampling circuitry.

A method for transmitting data advantageously reduces cross-talk in high-speed data transmission. The method comprises receiving an input data word, encoding the input data word into a code word, and driving the code word on to an interconnect for transmission. The code word is generating using a balanced coding scheme, and the interconnect is a single-ended, twisted-wire interposer interconnect. A receiver circuit decodes the code word to generate an output data word.