On-package multiprocessor ground-referenced single-ended interconnect

A processor, single-ended technology, applied in the direction of electrical digital data processing, instruments, static memory, etc., can solve the problems of low cost, chip signaling technology can not efficiently support multi-processing performance targets, etc.

Active Publication Date: 2014-09-17
NVIDIA CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In many cases, the die area associated with highly integrated multi-core processors is well above the feature cost knee (knee), which results in disproportionate cost inefficiencies associated with multi-core processors
Alternatively, computing systems

Method used

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  • On-package multiprocessor ground-referenced single-ended interconnect
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  • On-package multiprocessor ground-referenced single-ended interconnect

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Embodiment Construction

[0031] Techniques are provided for high-speed single-ended signaling between different chips making up a system-on-package device. The ground-referenced drivers deliver pulses with polarities determined by corresponding logic states. The pulses traverse the signal path and are received by a ground-referenced amplifier, which amplifies the pulses for interpretation as conventional logic signals. A set of ground-referenced drivers and ground-referenced amplifiers implement a high-speed interface configured to interconnect different chips making up a system-on-package device. The high speed communication enabled by ground reference signaling advantageously improves the bandwidth between different chips within a system-on-package device, which enables higher performance and higher density systems than provided by conventional signaling techniques .

[0032] Embodiments of the invention implement a system that includes a plurality of different processor chips, one or more memory ...

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Abstract

A system of interconnected chips comprising a multi-chip module (MCM) includes a first processor chip, a second processor chip, and an MCM package configured to include the first processor chip, the second processor chip, and an interconnect circuit. The first processor chip is configured to include a first ground-referenced single-ended signaling (GRS) interface circuit. A first set of electrical traces fabricated within the MCM package and configured to couple the first GRS interface circuit to the interconnect circuit. The second processor chip is configured to include a second GRS interface circuit. A second set of electrical traces fabricated within the MCM package and configured to coupled the second GRS interface circuit to the interconnect circuit.

Description

[0001] Statement of Rights [0002] This application was made with United States Government support under Agreement No. HR0011-10-9-0008 awarded by DARPA. The US Government has certain rights in this invention. This application is a continuation-in-part of U.S. Application Serial No. 13 / 844,570 (Attorney Docket NVIDP811 / SC-13-0072-US1), filed March 15, 2013, the entire contents of which are incorporated by reference Incorporated into this article. technical field [0003] The present invention relates to multiprocessor architectures, and more particularly, to on-package multiprocessor ground referenced single-ended interconnects. Background technique [0004] Successive generations of computing systems typically require increasing levels of performance and integration. A typical computing system includes a collection of central processing units (CPUs), graphics processing units (GPUs), high capacity memory subsystems, and interface subsystems. A collection of interface ...

Claims

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Application Information

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IPC IPC(8): G06F13/40
CPCH04L25/0276G11C7/10H05K1/11H04L25/028H04L25/0292
Inventor 威廉·J·达利布鲁切克·库都·海勒尼约翰·W·波尔顿托马斯·黑斯廷斯·格里尔三世卡尔·托马斯·格雷
Owner NVIDIA CORP
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