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189results about How to "Reduce decoding time" patented technology

Quantum error correction decoding method and device based on neural network, and chip

The invention discloses a quantum error correction decoding method and a quantum error correction decoding device based on a neural network, and a chip, which relate to the technical field of artificial intelligence and quanta. The quantum error correction decoding method comprises the following steps of: acquiring error symptom information of a quantum circuit; performing block feature extractionon the error symptom information through using a neural network decoder to obtain feature information; and subjecting the feature information to fusion decoding processing through using the neural network decoder to obtain error result information, wherein the error result information is used for determining error data quantum bits and corresponding error types in the quantum circuit. According to the quantum error correction decoding method and the quantum error correction decoding device, a block feature extraction mode is adopted, the number of channels of the feature information obtainedby each feature extraction is reduced, and the input data of the next feature extraction is reduced, thereby being conductive to reducing the number of feature extraction layers in the neural networkdecoder, further reducing the depth of the neural network decoder, shortening the decoding time of the neural network decoder correspondingly, and satisfying the requirement of real-time error correction.
Owner:TENCENT TECH (SHENZHEN) CO LTD

Rapid PBCH (physical broadcast channel) decoding method for LTE (long term evolution)

The invention discloses a rapid PBCH (physical broadcast channel) decoding method for LTE (long term evolution). The rapid PBCH decoding method includes the steps of recording corresponding address relation before and after one hundred and twenty data sub-blocks are interleaved to obtain the position of a to-be-interleaved datum after sub-block interleaving and rate matching and a PBCH deblocked sub-block interleaved corresponding relation table indicating positions of one hundred and twenty bits of an encoded tail biting convolution code after the sub-block interleaving; performing deblocked rate matching and deblocked sub-block interleaving, wherein in the PBCH deblocked sub-block interleaved corresponding relation table, the first column indicates the positions of the first to the eighth encoded bits after the sub-blocking interleaving, the second column indicates the ninth to the sixteenth encoded bits after the sub-blocking interleaving, and so on, and the fifteenth column indicates the one hundred and thirteenth to the one hundred and twentieth encoded bits after the sub-blocking interleaving. The rapid PBCH decoding method for the LTE and a structure for decoding a PBCH of the LTE are simplified, PBCH decoding time on the premise of reaching maximum likelihood decoding performance is shortened, resource consumption for PBCH decoding is saved and realizing complexity is reduced.
Owner:MEDIATEK INC

Method for decoding tail biting convolution codes of PBCH (physical broadcast channel) decoding in LTE (long term evolution)

The invention discloses a method for decoding tail biting convolution codes of PBCH (physical broadcast channel) decoding in LTE (long term evolution). A tail biting convolution decoder starts computing path metric from the starting position of a CRC (cyclic redundancy check) field, and a start state for computation of the path metric is zero constantly, and the computation of the path metric is separated into two situations: when SFN (system frame number) in an MIB (master information block) is unknown, computation of the path metric is ended at the sixth bit of a Spare bit field, a starting state of tracing back is zero, thirty-six decoding results are generated by the tail biting convolution decoder, and a PBCH decoding result finally with forty bits is formed by adding four '0' at the tail end of the thirty-six decoding results; when the SFN in the MIB is given, computation of the path metric is ended at the sixth bit of an SFN bit field, a starting state of tracing back is determined by the first six bits in the SFN field, twenty-eight decoding results are generated by the tail biting convolution decoder, and the PBCH decoding result finally with forty bits is formed by adding the last two bits of the SFN and ten '0' at the tail end of the twenty-eight decoding results.
Owner:MEDIATEK INC

Sign character extracting module and method

The invention provides a sign character extracting module applied to a barcode identifying device, comprising a bar and blank boundary storer, a boundary counter, a width calculating unit and a control logic unit, wherein the bar and blank boundary storer is used for storing the bar and blank boundaries of bar codes; the boundary counter is used for counting the quantity of the bar and blank boundaries stored by the bar and blank boundary storer; the width calculating unit is used for calculating the total width of the bar and blank boundaries stored by the bar and blank boundary storer to obtain the combined width value of the stored bar and blank boundaries; and the control logic unit is used for acquiring the bar and blank boundary number and the bar and blank width of the sign characters of the bar codes and then judging according to the quantity of the bar and blank boundaries and the combined width value of the stored bar and blank boundaries as well as the bar and blank boundary number and the bar and blank width of the sign characters of the bar codes to remove interference boundaries in the bar and blank boundaries. The invention also provides a sign character extracting method. The sign character extracting module and method can accomplish the work of removing the interference boundaries when acquiring the bar and blank boundaries, thereby quickening the decoding speed of the bar codes and shortening the decoding time.
Owner:NEWLAND DIGITAL TECH CO LTD
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