6results about How to "Reduce scheduling overhead" patented technology

The invention discloses a global nerve drawing method and system based on a programmable rasterization engine, and belongs to the technical field of computer graphics, and the method comprises the steps: at the programmable rasterization engine, analyzing a rasterization descriptor according to a rasterization instruction, and extracting vector microoperation and control parameters; maintaining a task state machine according to the parameters and distributing a control signal, selecting an execution entry from a vector kernel table according to the control signal, and instantiating an operation into a parallel vector thread; in a vector thread execution process, tracking data dependence of a vector register and a synchronization state of a direct memory access unit, executing vector loading / storage operation so as to carry data between the register and an on-chip shared memory according to the data dependence and the synchronization state, and dynamically scheduling vector micro-operation to an execution component so as to complete rasterization calculation; and outputting a result to the neural rendering network to complete global neural rendering. According to the method, the multi-representation neural rendering load can be uniformly and efficiently supported on the AI accelerator, the memory access overhead is remarkably reduced, and the calculation efficiency is improved.

This invention relates to the field of high-performance embedded real-time operating system application technology, and provides a method for task processing and human-machine interface processing on a display console based on VxWorks SMP, including: S1: Building a display console with a computer installed, configuring various control components and a display, and using the VxWorks SMP system to concurrently execute the task processing and human-machine interface processing functions that traditionally require two separate computers on the display console on this computer; S2: Developing and generating system-related project files using VxWorks development tools, and allocating and configuring task processing threads, human-machine interface processing threads, and control response underlying processing tasks, while configuring inter-task cooperation and protection mechanisms; S3: Writing a script program, guided by the VxWorks system, to load the control response underlying processing task binding project, task processing thread project, and human-machine interface processing thread project step by step. This solves the difficulty of concurrent operation of display console task processing and human-machine interface processing in VxWorks SMP.

The application discloses a kind of double host electronic glasses and its image acquisition, processing and display method, belong to image processing technical field, a kind of double host electronic glasses, including: glasses frame, monocular vst perspective unit and the power supply unit compatible with monocular vst perspective unit, the monocular vst perspective unit is equipped with two groups, and two groups monocular vst perspective unit respectively independently handles the image of left and right eyes, the monocular vst perspective unit includes, display component, the display component includes optical module and micro display screen;Sampling component, the sampling component includes corresponding camera module with display component;Soc host unit, the Soc host unit undertakes corresponding monocular image processing task;Realize the frame level synchronous display and the relatively synchronous display of degradable under the premise of not forwarding image data of double eyes, to ensure that electronic glasses can still maintain at least single eye real-time picture output under abnormal condition, high-speed data link is equipped between the Soc host unit.

The present specification relates to the technical field of virtual machines, and provides a virtual machine configuration method and device based on C86 architecture. The method comprises: generating first kernel cluster distribution information according to system information of a host computer; forming an optimization strategy according to the first kernel cluster distribution information and a preset quantization strategy; and obtaining virtual machine configuration information by using the optimization strategy. By the embodiment of the present specification, the scheduling overhead of the virtual machine can be reduced.

A processor and electronic equipment are applied to the field of data processing. The processor includes a scaling factor processing module including a smoothing pre-processing unit configured to receive the first tensor, the second tensor, and a smoothing control parameter, and a processing unit configured to process the first tensor and the second tensor by a plurality of arithmetic logic units and special function units in the processor. Executing smoothing operation of the first tensor and the second tensor to obtain a third tensor and a fourth tensor; the processing unit is configured to determine scaling factors of the third tensor and the fourth tensor and execute matrix multiplication and accumulation operation using the scaling factors based on the scaling factors of the third tensor and the fourth tensor to obtain a matrix multiplication operation result. The processor provides efficient smoothing preprocessing hardware, the processing does not need to be executed in special hardware devices such as a vector core, hardware-level efficient execution of smoothing preprocessing is achieved, hardware resource scheduling overhead and calculation delay are effectively reduced, and hardware execution efficiency is improved.

The embodiment of the invention provides a coding method, a hardware accelerator and a system on chip, and the method comprises the steps: determining a cardinal number frequency corresponding to each to-be-coded cardinal number obtained by mapping each input symbol through a frequency extraction module in the hardware accelerator; generating a target Huffman tree through a code generation module in the hardware accelerator based on the target sorting result of the cardinal number frequency corresponding to each cardinal number to be coded; and generating a compressed data stream through an encoding module in the hardware accelerator based on a target encoding result obtained by dynamically encoding each symbol to be encoded in the input data stream. And constructing a Huffman tree structure according to the target sorting result, so that the high-frequency cardinal number corresponds to the short code and the low-frequency cardinal number corresponds to the long code. And dynamically coding the input data stream based on the target Huffman tree to generate a compressed data stream, thereby realizing rapid coding conversion. The whole coding process is efficiently and cooperatively completed in a hardware accelerator, so that the data transmission and software scheduling overhead is reduced, and the data compression speed and performance are improved.