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Hardware method for memory management core related to schedule performance

A memory management and hardware-based technology, applied in the field of hardware-based process memory management cores, can solve problems such as tampering and insufficient security, reduce overhead, eliminate the possibility of malicious tampering, and ensure complete accuracy and reliability. Effect

Inactive Publication Date: 2009-09-23
ZHEJIANG UNIV
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  • Description
  • Claims
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AI Technical Summary

Problems solved by technology

Moreover, software exists in memory and is easily tampered with by malicious codes. Although security protection technologies emerge in endlessly, compared with hardware units that implement the same function, the security is insufficient.

Method used

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  • Hardware method for memory management core related to schedule performance

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Embodiment Construction

[0037] The present invention will be further described below in conjunction with drawings and embodiments.

[0038] First explain the nouns used and the premises used in some technical designs:

[0039] PID: process number, 4bit, 0 is not used, so it can represent up to 15 processes;

[0040] PID_TO_PCB: process number and page table base address conversion table;

[0041] suc: the return value of each operation in the output signal, 1 for success and 0 for failure;

[0042] VA: Logical address in the input signal, a total of 22 bits, page size 4K bytes;

[0043] PA: The physical address in the output signal, with a total of 22 bits and a page size of 4K bytes;

[0044] last_pid: the process number of the last running or about to be switched away;

[0045] curr_pid: the number of the process currently running or about to run;

[0046] TLB: Translation Look-aside Buffer, used to speed up page table lookup;

[0047] The method of hardwareizing the memory management core di...

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Abstract

The invention discloses a hardware method for process memory management core related to schedule performance. The method hands over the process memory management directly related to the schedule performance in an operating system, including the functions of creating, deleting and switching of process page tables, virtual address mapping, switching of the virtual address to the physical address, to hardware for completion, thus reducing the expenditure of process switching while scheduling and improving the efficiency when in process switching. The hardware method can be utilized for other parts of the operating system. The hardware method realizes process memory management, reduces the expenditure of process switching and improves the efficiency when in process switching, hands over the functions which are originally realized by the software code to a hardware unit for completion, eliminates the possibility that a certain part of the operating system is modified maliciously and guarantees the complete correctness and reliability of processing.

Description

technical field [0001] The invention relates to a hardware operating system, in particular to a hardware process memory management core. Background technique [0002] With the popularity of computer applications in people's lives, it is becoming more and more important to rely on computers for automated management, control, calculation and service processing. Especially in the fields of finance, industry, and control, in addition to ensuring the reliability and safety of computers, the requirements for processing speed and response time efficiency are also very important. [0003] At the same time, due to the rapid development of the Internet, large servers and some machines dedicated to real-time task processing require a very high speed of service response and request processing. However, the use of software limits further speed improvements. The operating system as a software manager has actually become a bottleneck for speed improvement. Therefore, many improved versi...

Claims

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Application Information

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IPC IPC(8): G06F9/48
Inventor 陈天洲缪良华张楠陈剑汪达舟
Owner ZHEJIANG UNIV
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