Hybrid task scheduling method of directed acyclic graph (DGA) based reconfigurable system

Abstract

The invention discloses a hybrid task scheduling method of a directed acyclic graph (DGA) based reconfigurable system. The hybrid task scheduling method includes decomposing an application into multiple tasklets described by DGA, and scheduling the tasklets through a scheduler; allowing software tasks to enter a queue Q1, and calculating the software tasks in the queue Q1 according to CPU idling condition and scheduling priority after the software tasks are managed through a task manager; allowing hardware tasks to enter a queue Q2, and further allowing the hardware tasks to enter a queue Q3 if the hardware tasks in the queue Q2 are capable of reutilizing a reconfigurable resource, otherwise, keeping the hardware tasks queuing up in the queue Q2 according to the priority and then configuring and loading through a loader; completing the process of configuring and loading or allowing the tasks in the queue Q3 to enter a queue Q4, allowing the tasks in the queue Q4 to enter a queue Q5 after the tasks are managed via the task manager, then running the tasks according to the priority, sequentially circulating until finishing running of all the tasks, and finally feeding back the total running time. The Q1 refers to the software task queue, the Q2 refers to the preconfigured hardware task queue, the Q3 refers to the configuration reuse queue, the Q4 refers to the configuration completion queue, and the Q5 refers to the running task queue. Configuration frequency is reduced by a configuration reuse strategy, so that the overall scheduling overhead is reduced.

Description

technical field

[0001] The invention relates to the field of reconfigurable computing, in particular to a dynamic reconfigurable task scheduling method. Background technique

[0002] Reconfigurable computing not only maintains the traditional hardware-based execution efficiency, but also maintains a variable architecture, which can adapt to the diverse needs of practical applications. It is a cutting-edge technology today. It breaks the boundaries between software and hardware, and its performance is between microprocessors and application-specific integrated circuits, and it is widely used in the field of high-performance computing.

[0003] The research on reconfigurable computing technology has a strong dependence on the development of reconfigurable logic devices. Dynamic reconfigurable devices represented by FPGA are composed of a series of configurable logic blocks CLBs (Configurable Logic Blocks), which makes It has the ability to be partially reconfigured. It can a...

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