Device and method for buffering data in dynamic reconfigurable array

Abstract

The invention provides a device and a method for buffering data in a dynamic reconfigurable array, wherein the device concretely comprises an input data buffer, a processing unit array, a general purpose register file and an output data buffer, wherein the input data buffer is used for reading in data from an external storage, buffering the data, and outputting the data to the processing unit array when needed; the processing unit array is used for reading in data from the input data buffer or the general purpose register file, and carrying out logical operation on the data; the general purpose register file is used for being interconnected with the processing unit array, reading in data from the processing unit array, buffering the data, and outputting the data to the processing unit array when needed; and the output data buffer is used for buffering result data processed by the processing unit array and reading out the data to the external storage when needed. According to the invention, the times for reading and writing the data between the dynamic reconfigurable array and the external storage can be reduced, and thus the performance of a dynamic reconfigurable processor is improved.

Description

technical field [0001] The present application relates to the technical field of embedded systems, in particular to a device and method for caching data in a dynamically reconfigurable array. Background technique [0002] Dynamic reconfigurable processor is a new type of processor architecture, which combines the flexibility of software and the efficiency of hardware. Compared with traditional single-core microprocessors, it can not only change the control flow, but also change the data path. It has the advantages of high performance, low power consumption, good flexibility, and good scalability, and is especially suitable for processing computationally intensive algorithms, such as media processing, pattern recognition, and baseband processing. Therefore, dynamically reconfigurable processors have also become an important development direction of the current processor structure, such as the ADRES processor of the European Microelectronics Center (IMEC) and the CHESS process...

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Problems solved by technology

[0004] Due to the limitation of the scale of the reconfigurable array, it is very easy for part of the structure of the algorithm to be placed in the array. At this time, it is required to divide the flow graph of this type of algorithm and increase the number of configurations. The data between configurations is related. The last time The calculation results of the configuration need to be written into the external memory first, and then read from the external memory when the configuration calls the data next time. The read and write speed of the external memory is relatively slow, which affects the computing performance of the dynamically reconfigurable processor.

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