3results about How to "Reduce Decoding Latency" patented technology

This invention discloses a layered decoding method and apparatus for LDPC frames based on mutual information, relating to the field of digital signal transmission in the physical layer of wireless communication. The method includes the following steps: 1) Calculating the LLR value of a given codeword to be decoded, and performing Q-ratio specific-point quantization to maximize mutual information on the entire frame's LLR value; 2) Calculating the PP value of the Q-ratio specific-point quantized LLR value according to Bayes' formula; 3) Layering the PP values ​​of the LLR values ​​of the data to be decoded according to the coefficients of the parity check matrix H; 4) Calculating the information within the information node; 5) Performing parity check node update calculations according to the PMS decoding algorithm to obtain the information value outside the parity check node; 6) Updating the information node using the information value outside the parity check node; 7) Symbol decoding; 8) Calculating the syndrome according to H. If the result of the syndrome is 0 or the maximum number of iterations is reached, outputting the three-frame codeword result; otherwise, returning to step 3) for the next decoding iteration. This invention can effectively improve the decoding processing speed of each frame.

The invention discloses a dynamic error correction method suitable for a three-dimensional NAND flash memory, a controller and a storage system, and belongs to the technical field of semiconductor storage, and the method comprises the following steps: a coding stage: carrying out polar code coding on data to be written into the three-dimensional NAND flash memory to obtain a code word sequence with the length of N; in the decoding stage, the LLR value of each bit is calculated for the data with the length of N read from the three-dimensional NAND flash memory; after setting the list length of the SCL decoding algorithm, inputting the N-bit LLR value into the SCL decoding algorithm to realize decoding; the step of setting the list length of the SCL decoding algorithm comprises the following steps: acquiring bit error rates of the SCL decoding algorithm under different list lengths under the current original bit error rate of the three-dimensional NAND flash memory, screening the list length with the bit error rate lower than a preset performance threshold, and setting the list length of the SCL decoding algorithm as the screened minimum length. The method adapts to the error characteristic of the three-dimensional NAND flash memory, and the overhead can be reduced under the condition of ensuring that the error correction requirement is met.

The invention discloses a two-dimensional LDPC (Low Density Parity Check) error correction method suitable for a flash memory, a flash memory controller and storage equipment, and belongs to the technical field of flash memories, and the encoding steps are as follows: after performing two-dimensional LDPC encoding on every K information bits in a flash memory page, storing obtained check bits in an OOB area of the flash memory page to complete encoding of the flash memory page; the two-dimensional LDPC coding comprises the following steps: equally dividing K information bits into B information bit blocks with the size of k, and taking every c continuous information bit blocks as one row in an information matrix to obtain an information matrix with r rows and c columns; for each row in the information matrix, coding by using a first LDPC code to generate a transverse check bit corresponding to each row; and for each column in the information matrix, coding is carried out by using the second LDPC code, and a longitudinal check bit corresponding to each column is generated. According to the method, the decoding delay of the flash memory system adopting the LDPC code can be remarkably reduced on the premise of ensuring that redundant space is not additionally increased.