12results about "Error correction/detection using single space coding" patented technology

A system and method for detecting an angle of arrival (AoA) of incident waves are disclosed. An array of wave sensors each transduce incident waves into an electrical signal, which is then provided an additional phase shift that varies between sensors. Electrical signals from adjacent wave sensors, having different phase shifts, are coupled via a phase detector to classify the incident waves into “zero” and “one” AoA regions for that sensor pair. The outputs from many such phase detectors are combined to divide the space facing the array into many subregions, each subregion being associated with a unique codeword. Incident waves cause detection of codewords, that are decoded according to error detection and correction techniques, such as selecting, from a list, the codeword having a minimum Hamming distance to a received codeword. The decoder then outputs data indicating an AoA subregion associated with the decoded codeword.

Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a transmitter may generate multiple encoded bits using a polar encoder. The transmitter may separate the multiple encoded bits into N layers for a multiple-input-multiple-output (MIMO) transmission. The transmitter may select V layer pairs from the N layers, each layer pair of the V layer pairs including a respective first layer and a respective second layer from the N layers. The transmitter may group, for each layer pair of the V layer pairs, a first M symbol bits of the respective first layer and a second M symbol bits of the respective second layer to generate multiple bit pairs. Each bit pair includes a respective first bit of the first M symbol bits and a respective second bit of the second M symbol bits. Numerous other aspects are described.

The invention relates to a data interleaving method with n core processors, each associated with a local memory whose output portion is strictly smaller than the interleaving length L, comprising: implementing, N times, the interleaving algorithm of length L on said input sequence, the interleaved input sequence being the union of subsequences S_1, …, S_N; the ith implementation, i = 1 to N, of the interleaving being performed by one of the n cores, then storing only S_i in said local memory portion of said core; transferring S_i to a memory external to the processor core. Figure for the abstract: Fig. 2

Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a transmitter may generate multiple encoded bits using a polar encoder. The transmitter may separate the multiple encoded bits into N layers for a multiple-input-multiple-output (MIMO) transmission. The transmitter may select V layer pairs from the N layers, each layer pair of the V layer pairs including a respective first layer and a respective second layer from the N layers. The transmitter may group, for each layer pair of the V layer pairs, a first M symbol bits of the respective first layer and a second M symbol bits of the respective second layer to generate multiple bit pairs. Each bit pair includes a respective first bit of the first M symbol bits and a respective second bit of the second M symbol bits. Numerous other aspects are described.

This disclosure provides a signal verification method, apparatus, device, and medium performed by an electronic device, which can be applied to the field of communication technology. The method includes: reading an original codeword set from a register; performing K partial verifications based on the original codeword set to obtain a signal verification result; wherein the k-th partial verification process includes: performing a quasi-cyclic shift on the (k-1)-th updated codeword set to obtain an extended updated codeword set, and constructing an extended updated codeword matrix based on the extended updated codeword set; extracting random rows and columns from the extended updated codeword matrix to obtain a shortened codeword matrix; performing a Gaussian row transform on the shortened codeword matrix to obtain a sampling verification matrix, and extracting low code weight vectors from the sampling verification matrix; constructing a k-th partial decoding matrix related to the k-th partial verification based on a sparse vector set; and using the k-th partial decoding matrix to perform partial verification on the (k-1)-th updated codeword set to obtain the k-th updated codeword set.

Methods, systems, and devices for wireless communications are described. In some examples, a transmitting device, such as a user equipment (UE) or a network entity, may encode an information bit vector into multiple code blocks using a polar code partitioned into multiple sub-blocks having a same block length in accordance with a polar transformation associated with a modulation scheme. In some examples, each code block of the multiple code blocks may be encoded using a respective sub-block of the multiple sub-blocks. Additionally, the transmitting device may interleave respective bits of each code block of the multiple code blocks using a respective interleaver of multiple interleavers. As such, the transmitting device may transmit the respective interleaved bits of each code block of the multiple code blocks over a respective bit channel of multiple bit channels, where each bit channel of the multiple bit channels is associated with a respective reliability.

This application provides a data transmission method and apparatus. The method includes: encoding one or more coding units with an external code to obtain first redundant data; and transmitting the first redundant data on a first resource, wherein the first resource is predefined or configured by an access network device. By predefining the resource for carrying the redundant data obtained by the external code encoding, or by configuring the resource separately for the redundant data by the access network device, a first communication device can map the redundant data onto the given resource for transmission, giving the redundant data a clear resource boundary, thereby reducing the impact on the original information in certain scenarios. Furthermore, by mapping the redundant data onto the given resource for transmission, it is convenient to utilize the redundancy characteristics of the redundant data to reuse, punch holes in, or counteract interference on the resources occupied by the redundant data, thereby improving spectrum utilization.

Embodiments of the present invention provide adaptive transport block size determination and code block segmentation methods, systems and apparatus. In the method, segmentation of a plurality of information bits into a plurality of code blocks can be based on a maximum code length and / or a maximum information block size. The plurality of code blocks can then be encoded into a plurality of codewords. The adaptive transport block size determination and code block segmentation method can be used in scenarios requiring flexible or multiple code lengths. The method can reduce coding complexity and improve performance.

This disclosure provides an error correction coding method and system for near-optimal binary arrays, relating to the technical field of encoders or decoders. The method includes: acquiring a binary array and preprocessing it; anchoring and locating the preprocessed binary array, transforming global location into local error correction for rows and columns; applying VT checksum constraints to the local error correction regions, introducing a main diagonal checksum equation for the array's rows / columns, enabling the recovery of symbols in missing rows or columns during decoding; recovering affected sub-blocks and determining precise deletion indices based on a VT-type signature error correction mechanism; recovering the remaining symbols in the missing rows / columns using the main diagonal checksum, thus completing the full array decoding. This disclosure approximates the information theory lower bound on redundancy as closely as possible while providing an engineering-practical coding process and complexity guarantee.

The invention relates to a data interleaving method with n core processor(s) each associated with a local memory whose part dedicated to the output of the interleaving is of a size strictly less than the interleaving length L, comprising: implementation, N times, of the interleaving algorithm of length L on said input sequence, the interleaved input sequence being the union of sub-sequences S_1, ..., S_N; the ith implementation, i = 1 to N, of the interleaving being carried out by one of the n core cores, then storage in said part of local memory of said core of only S_i; transfer of S_i into a memory external to the processor core.

An apparatus includes a decoder (32), a compressor (36) and a decompressor (40). The decoder decodes a codeword of an ECC in a sequence of decoding steps. In a given decoding step, the decoder attempts decoding a respective subset of bits of the codeword by: (a) receiving a combination of (i) channel soft metrics and (ii) intermediate soft metrics that have gone through one or more previous decoding steps, for the bits in the subset, (b) attempting to decode the subset by processing the channel soft metrics and the intermediate soft metrics, and (c) updating one or more of the intermediate soft metrics. The compressor converts at least some of the intermediate LLRs belonging to a subset into a joint compressed representation. The decompressor decompresses the joint compressed representation to produce decompressed intermediate soft metrics, and provides the decompressed intermediate soft metrics for use in subsequent decoding steps.