High-speed Turbo decoding method and device

A decoding device and decoding technology are applied in the field of high-speed turbo decoding methods and devices, which can solve the problems of prolonged decoding delay, increased cost, large decoding delay, etc., and achieve high decoding performance and shorten decoding delay. Effect

Active Publication Date: 2010-05-12
HONOR DEVICE CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] In the process of realizing the present invention, the inventors found that there are at least the following problems in the prior art: the training cycle and the state operation cycle are arranged in series, and the use efficiency of logic resources is low; the decoding cycle is directly related to the training length, and the training length increases. It directly leads to longer decoding delay; when the performance requires a longer training length, the decoding delay becomes very large; if you want to improve the throughput of the decoder, you need to increase the logic resources exponentially, which significantly increases the cost

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  • High-speed Turbo decoding method and device

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Embodiment 1

[0022] Such as figure 1 Shown is a schematic flow chart of a high-speed turbo decoding method provided by Embodiment 1 of the present invention, and the method includes the following steps:

[0023] S101: Receive a data code block to be decoded. The step of receiving the data code block belongs to the prior art, and will not be repeated here.

[0024] S102: Divide the data code block to be decoded into multiple sub-data blocks in units of a sliding window length, where the length of the sliding window is generally in units of bits, and its value can be preset. In this embodiment, these sub-data blocks need to be stored in a storage unit to provide data sources for subsequent various decoding operations, such as training operations, backward state operations, forward state operations, and The outer information operation uses soft information such as systematic bit information, check bit information, and outer information of the data code block.

[0025] S103: Perform parallel...

Embodiment 2

[0030] Such as figure 2 Shown is a schematic flow chart of a high-speed turbo decoding method provided by Embodiment 2 of the present invention, and the method includes the following steps:

[0031] S201: Receive a data code block to be decoded.

[0032] S202: Divide the to-be-decoded data code block into multiple sub-data blocks in units of a sliding window length.

[0033] Steps S201 and S202 are similar to those in Embodiment 1, and will not be repeated here.

[0034] S203: Alternately store the calculation information in the sub-data block in three mirror memories whose capacity is the length of the sliding window. As an embodiment of the present invention, the operation information refers to systematic bit information, parity bit information and external information in the sub-data block.

[0035] The inventor finds in the process of realizing the present invention, to realize the parallel operation of the training operation, the backward state operation, the forward ...

Embodiment 3

[0063] Such as Figure 4 A schematic structural diagram of a high-speed turbo decoding device provided in Embodiment 3 of the present invention, the device includes: a receiving unit 410, a code block division unit 420, and a parallel operation unit 430, wherein the code block division unit 420 is connected with the reception unit 410 and the parallel operation unit 430 respectively. The parallel computing unit 430 is connected. It should be pointed out that the present invention describes the Turbo decoding device from the perspective of logical functional units. In practice, the Turbo decoding device is not limited to having these units, but as long as it has these units function.

[0064] The receiving unit 410 is configured to receive the data code block to be decoded, and the reception of the data code block belongs to the prior art, so it will not be repeated here.

[0065] The code block dividing unit 420 is used to divide the data code block to be decoded received by ...

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Abstract

The embodiment of the invention provides a high-speed Turbo decoding method and a device thereof, wherein the method comprises the following steps: receiving a data code block to be decoded; dividing the data code block to be decoded into a plurality of sub-data blocks by taking length of a sliding window as a unit; and conducting parallel operations including training operation, backward state operation, forward state operation and external information operation during Turbo decoding on the sub-data blocks to obtain the decoding result. The embodiment of the invention has the following beneficial effect: by conducting the parallel operations including the training operation, the backward state operation, the forward state operation and the external information operation to the sub-data blocks, decoding delay is shortened while keeping high decoding performance.

Description

technical field [0001] The invention relates to the communication field, in particular to a high-speed Turbo decoding method and device. Background technique [0002] At present, the downlink data rate of the HSPA+ (high speed packet access plus, enhanced high-speed packet access technology) system adopting MIMO (mult_in and mult_out) technology can reach 42 Mbps. Such a high data throughput rate is a huge challenge for Turbo decoding, which is a key link in the downlink decoding chain. [0003] The Turbo decoder is an important functional component in the error control mechanism-HARQ (hybrid automatic request equipment, hybrid automatic repeat request mechanism) defined in the HSPA+ related protocol 3GPP TS 25.212. The soft bit data obtained in the demodulator often needs to be After multiple iterations of decoding in the Turbo decoder, its decoding delay depends not only on the amount of data, but also on the required decoding performance and decoder structure. At the sa...

Claims

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Application Information

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IPC IPC(8): H04L1/00H04L29/08
Inventor 张家佶范文奇游治朱芳菲
Owner HONOR DEVICE CO LTD
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