Method for reducing LDPC decoding delay based on error characteristics of flash memory pages

A flash memory page and decoding technology, applied in the direction of response error generation, error detection/correction, redundant code error detection, etc., can solve the problem of large decoding delay gap

Active Publication Date: 2017-11-24
HUAZHONG UNIV OF SCI & TECH
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Problems solved by technology

[0004] However, the existing LDPC error correction algorithm has a serious problem in ensuring the data reliability of MLC NAND flash memory, that is, when using the existing LDPC decodin

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  • Method for reducing LDPC decoding delay based on error characteristics of flash memory pages
  • Method for reducing LDPC decoding delay based on error characteristics of flash memory pages

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[0054] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not constitute a conflict with each other.

[0055] Design structural drawing of the present invention is as figure 1 As shown, after the bit data is encoded by the LDPC encoder, the obtained codeword is transferred to the page register, first written to the MSB page of the MLC NAND flash memory, and the obtained codeword is written to the LSB page. As the bit data storage time changes, the electrons stored in the MLC NAND flash memory un...

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Abstract

The invention discloses a method for reducing an LDPC decoding delay based on error characteristics of flash memory pages. As the manufacturing process of an MLC NAND flash memory is improved, the size of memory cells becomes smaller and coupling interference between the cells becomes stronger, as a result, a high bit error rate is caused, and the high bit error rate seriously affects the reliability of data. LDPC codes with a high error correction capability are widely used to ensure the data reliability. However, when the LDPC codes are used, an MSB page and an LSB page of the MLC NAND flash memory have unbalanced decoding delays, the decoding delay of the LSB page is higher than the decoding delay of the MSB page, and since the LSB page has a quite high bit error rate, the reading performance of an MLC flash memory is poor. According to the invention, favorable information is provided for LSB page decoding according to a decoding result of the MSB page and a save error mode so that the decoding delay of the LSB page is reduced, the decoding delay gap between the two pages is narrowed, and the reading performance of the MLC flash memory is improved.

Description

technical field [0001] The invention belongs to the technical field of solid-state disk storage, and more particularly relates to a method for reducing LDPC decoding delay based on a page fault mode of a flash memory. Background technique [0002] NAND flash memory has the characteristics of large capacity, low energy consumption and non-volatility, and is widely used in computer storage systems and consumer electronics products. Through the improvement of manufacturing process, the reduction of unit size and the use of multi-bit technology, each unit stores more data bits, such as multi-level cell (Multi-Level Cell, referred to as MLC) NAND flash stores two bits per unit, which improves the The capacity of the flash memory. However, the strong coupling interference between units and the occurrence of storage errors cause high bit error rates, reducing data reliability. [0003] In view of this, error-correcting codes are currently widely used to reduce the bit error rate ...

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Application Information

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IPC IPC(8): H03M13/11G06F11/10
CPCG06F11/1012G06F11/1068H03M13/1111
Inventor 吴非谢长生张猛崔兰兰
Owner HUAZHONG UNIV OF SCI & TECH
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