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777results about How to "Save hardware resources" patented technology

Method for designing AES (Advanced Encryption Standard) encryption chip based on FPGA (Field Programmable Gate Array) and embedded encryption system

The invention discloses a method for designing an AES (Advanced Encryption Standard) encryption chip based on an FPGA (Field Programmable Gate Array), which is designed for aiming at the requirement of an embedded system. The AES encryption chip not only can be used in a manner of a solid chip but also used in a manner of a software module. Three operation modes of ECB (Electronic Code Book), CBC (Cipher Block Chaining) and CTR (Counter Technical Requirement) are supported simultaneously. All standards of the AES can be encrypted and decrypted. The byte replacement and the key expansion are carried out by using a look-up table optimization algorithm. A column mixed optimization structure is provided. Device resources are saved while the operation speed is ensured. An RAM (Random-Access Memory) can be configured as a cache of information and a key through double ports of the FPGA. A problem for storing a time sequence and data of other devices or equipment and the FPGA is resolved. Safe and reliable communication with an FPGA interface joins CRC (Cyclic Redundancy Check) error detection in a manner of a memory bus. The AES encryption chip has the advantages of high safety, high encryption and decryption speeds, low device resource requirement, low cost and the like. The AES encryption chip can be widely used in information technology industries of intelligent card systems, ATMs (Automatic Teller Machines), wireless local area networks, wireless sensor networks and the like.
Owner:BEIHANG UNIV

Broadband sub-matrix adaptive beamforming method based on sub-band decomposition

The invention discloses a broadband sub-matrix adaptive beamforming method based on sub-band decomposition, which mainly resolves the problem that computation burden in the prior art is high, and broadband interference signals cannot be processed and suppressed adaptively. The implementation process of the broadband sub-matrix adaptive beamforming method includes steps: 1) dividing a total matrix into a plurality of sub-matrixes, leading the sub-matrixes to be aligned with local beam pointing by the aid of microwave synthesis of a phase shifter, and obtaining sub-matrix synthesis data; 2) selecting a prototype filter and obtaining corrected analyzing and comprehensive filter banks via a cosinusoidal modulation filter bank; 3) under-sampling the sub-matrix synthesis data after the sub-matrix synthesis data pass through the analyzing filter banks, solving an adaptive weight in a narrow band and performing sub-band beamforming in the narrow band; and 4) up-sampling signals after sub-band beamforming, leading the up-sampling signals to pass through the comprehensive filter banks, and summating data of the comprehensive filter banks to obtain data after broadband adaptive beamforming. The broadband sub-matrix adaptive beamforming method has the advantages that the dimension of hardware is small, computation burden is low and broadband interference signals can be suppressed adaptively. In addition, the broadband sub-matrix adaptive beamforming method can be used for adaptive beamforming of a broadband phased array radar.
Owner:XIDIAN UNIV

Inverse operation method for lower triangle complex matrix with any order

The invention relates to an inverse operation method for a lower triangle complex matrix with any order. The inverse operation method comprises the following steps that (1) a reciprocal obtaining unit is set, and is used for carrying out reciprocal obtaining operation on a diagonal element of an N-order matrix L, and outputting a matrix obtained after reciprocal obtaining operation is accomplished; (2) a multiplication and accumulation unit is set and is used for receiving the matrix obtained after reciprocal obtaining operation is accomplished, and multiplication and accumulation operation is carried out on the first element to the (i-1)th element in the ith row in the matrix; (3) a reciprocal multiplication obtaining unit is set and is used for receiving the accumulation result corresponding to the elements in the ith row of the matrix, reciprocal obtaining operation is carried out on the accumulation result, and then the accumulation result processed through reciprocal obtaining operation is multiplied by a diagonal element in the ith row so that a matrix element of the ith row of an inverse matrix L-1 can be obtained. In the whole process, a plurality of multiplication and accumulation units are used for carrying out parallel calculation. The inverse operation method for the lower triangle complex matrix with any order has the advantages that the inverse operation of the lower triangle complex matrix with any order can be achieved, and restriction caused by the number of operation units does not exist; only the design of a multiply-accumulator with one plural adder and one plural multiplier is adopted, hardware resources are saved, and operation efficiency is ensured through an effective parallelization mode.
Owner:NANJING UNIV

Hardware realization method and system for artificial neural network algorithm

The invention provides a hardware realization method and a system for an artificial neural network algorithm, which overcome the defects of high cost and overlarge occupation of hardware resources of the prior hardware realization technology. The system comprises a top layer module, the top layer module consists of a plurality of neuron modules, pulse input ends of the neuron modules input given weight products, output ends of the neuron modules fit the given weight products into a Sigmoid function of a neutral network through a normal distribution random generator and a nonlinear converter, and then the Sigmoid function is converted into pulse to be output through a pulse converter. Compared with the prior realization technology, the hardware realization method and the system for the neural network algorithm avoid the embarrassment that a serial mode in the prior software realization is used to finish parallel computation, overcome the disadvantages of software realization, save a large amount of hardware resources due to the algorithm optimization, have lower cost due to the realization on an FPGA platform, utilize an optimized algorithm to avoid the difficulty that the Sigmoid function is difficult to realize by a hardware, and also save the hardware resources by using an accumulation mode.
Owner:UNIV OF SHANGHAI FOR SCI & TECH

System and method for correcting on-orbit amplitude phase of phased-array antenna

The invention relates to a system and method for correcting an on-orbit amplitude phase of a phased-array antenna. A signal output by a microwave signal source and used for correcting is transmitted through a beacon antenna in a phased-array near field and received by a certain channel to be detected of the phased-array antenna; the output signal is subjected to down-conversion and AD acquisition; amplitude and phase measurement of the signal can be completed through a signal processing module; finally, the measured amplitude and phase of the signal are subjected to data processing; obtaining of the amplitude and the phase of the channel to be detected is completed; and amplitude phase correction is completed. According to the invention, on the basis of the beacon in the phased-array near field, with the help of an interference cancellation principle, the amplitude phase measurement influence to the channel to be detected by leaking (multipath) signals can be eliminated; the accuracy of a measurement result is increased; the implementation principle is simple; system software resources are saved; in the aspect of implementing amplitude phase measurement, a single-channel amplitude phase measurement scheme is selected and used; an auxiliary reference channel is not adopted; and thus, system hardware resources and the cost are saved.
Owner:XIAN INSTITUE OF SPACE RADIO TECH

APF (Active Power Filter)parallel system and control method thereof

The invention discloses an APF (Active Power Filter) parallel system. The APF parallel system comprises a plurality of APFs connected with a power grid, and a detection control unit. High-voltage ends of direct current support capacitors of all the APFs are commonly connected, and low-voltage ends of the direct current support capacitors of all the APFs are commonly connected. The parallel system provided by the invention only needs a set of detection control equipment to control the plurality of APFs, thus, less hardware resource is occupied. Simultaneously, the invention further discloses a control method of the APF parallel system. The control method comprises the following steps of: (1) obtaining state information of the power grid, the loads and the parallel system; (2) extracting a current instruction from the load current; (3) calculating a current error signal; (4) performing repetitive control and PI (proportional integral) regulation on the current error signal to obtain a modulation signal; (5) forming a PWM (Pulse-Width Modulation) signal. The method provided by the invention has higher reactive compensation precision and harmonic suppression capability, and can effectively suppress system circulating current.
Owner:ZHEJIANG UNIV +1

Cross-platform Jave virtual machine of digital television middleware system

The invention discloses a cross-platform Jave virtual machine of a digital television middleware system, belonging to the technical field of communication. The cross-platform Jave virtual machine comprises an operating system and a device drive program based on a hardware platform, wherein a platform adaptation layer is arranged based on the operating system and the device drive program; and a core class library containing a Java virtual machine and a set-top box device installed in the middleware system is utilized based on the platform adaptation layer to build the Jave virtual machine which is at least formed by a class loading sub-system, a security management sub-system, an execution engine and a local method invoking interface sub-system functional module so as to provide an operation platform of the Java application and the service for the digital television middleware. The invention supports the China standard, is easy to transplant to the other standards, and has no relation with the hardware platform, unified resource management, no OS limitation on the quantity of operational Jave threads, more compact system structure, less occupied hardware resource and less limitation on the hardware platform.
Owner:商埃曲网络软件(上海)有限公司

Multimode support parallel multichannel fast frequency sweeping method and multimode support parallel multichannel fast frequency sweeping system

The invention relates to a multimode support parallel multichannel fast frequency sweeping method and a multimode support parallel multichannel fast frequency sweeping system. The system consists of four parts including a broadband radio frequency part, a multimode medium frequency part, a baseband frequency sweep algorithm part and a software configuration module, wherein the broadband radio frequency part is mainly used for carrying out analog amplification, filtering, frequency mixing, analog-to-digital (A/D) conversion and the like on the received radio-frequency signals; the multimode medium frequency party is mainly used for carrying out down-conversion treatment on digital intermediate frequency signals, wherein digital frequency mixing is carried out on the signals before down-conversion; the baseband frequency sweep algorithm part mainly comprises a frequency point detection module and a power calculation module; the frequency point detection module is used for rapidly and accurately judging frequency points, and the power calculation module is used for determining a main base station frequency point and a neighbor cell site frequency point; the software configuration module is used for carrying out online configuration on radio frequency and intermediate frequency by an upper computer, so that broadband radio frequency and multimode medium frequency are realized, and multiple communication systems are compatible. The multimode support parallel multichannel fast frequency sweeping system is capable of realizing rapid frequency sweeping of multiple communication modes such as global system for mobile communication (GSM), code division multiple access (CDMA), wideband code division multiple access (WCDMA), line termination equipment (LTE) and the like; the system is high in flexibility, rapid in speed, wide in application scope and cost-saving.
Owner:CHONGQING UNIV OF POSTS & TELECOMM

Method, equipment and system for reducing headset noise

The invention discloses a method, equipment and system for reducing headset noise, aiming at providing a method for reducing the headset noise without addition of hardware equipment and further saving the hardware equipment. The method comprises the following steps of: processing environment noise acquired by an MIC (Microphone) of a headset through a headset interface, an analog/digital conversion circuit, a digital filtering circuit, an audio decoder and a digital/analog conversion circuit of equipment to obtain reverse-phase environment noise corresponding to the environment noise; and overlaying the reverse-phase environment noise into an audio signal and transmitting the reverse-phase environment noise to the headset so that the reverse-phase environment noise and the environment noise heard by human ears can be cancelled out each other to realize noise reduction of the headset. By adopting the technical scheme disclosed by the invention, the headset noise can be reduced without improving the headset, or equipment connected with the headset, the procedure of reducing the headset noise is simplified, the hardware equipment is saved; and the hardware equipment does not need to be improved, thus the commonality and the flexibility of reducing the headset noise are improved.
Owner:QINGDAO HISENSE MOBILE COMM TECH CO LTD

Integrated processing system based on VPX platform and software design method thereof

The present invention discloses an integrated processing system based on a VPX platform and a software design method thereof. The system comprises a backboard provided with a plurality of slots, the system is mother-daughter board configuration based on a standard VPX bus, the system comprises a motherboard and a daughter board, the motherboard is an exchange interface board, the daughter board is an extension interface board, the motherboard and the daughter board are connected through an XMC connector, and the motherboard and the daughter board are communicated through an X4 SRIO bus; the slots can be inserted into a plurality of other board cards, the backboard can realize the communication of the motherboard, the daughter board and other board cards in the processing system; and a motherboard dual-core ARM Cortex<TM>-A9 processor PS and a daughter board dual-core ARM Cortex<TM>-A9 processor PS perform real-time operation of the system. The integrated processing system has rich extension capability, can satisfy application requirements of different scenes through replacing of daughter boards having different functions, has good, flexibility is wide in application range, can realize shelf performances of modules, and can rapidly build an integrated processing system aiming at a special guidance application background according to the application requirements.
Owner:THE GENERAL DESIGNING INST OF HUBEI SPACE TECH ACAD
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