38 results about "Hardware register" patented technology

The invention relates to the field of digital power supply control, and provides a parameterized digital control method and system suitable for a wide power range charging module, and the method comprises the steps: collecting an original sensor signal, constructing a slow working condition feature vector through adaptive-temperature drift compensation, and driving a physical constraint reference prediction model to generate a second baseline behavior parameter vector; monitoring a gate driving current by using a gate-drain capacitor, extracting a transient characteristic value, and quantifying the transient characteristic value into a ZVS quality factor; the slow working condition feature vector and the ZVS quality factor are fused, a correction vector is generated through an adaptive prediction model, a control parameter vector is generated in combination with a second baseline behavior parameter vector, and online updating is carried out according to feedback; executing hardware physical limit constraint according to the security constraint set, generating security parameters and abnormal flag bits, and writing the security parameters and the abnormal flag bits into a hardware register in a fixed-point manner after cooperating with ZVS quality factor arbitration. According to the method, physical constraint prediction and transient perception correction are fused, and a digital control system considering dynamic response, drift compensation and safety redundancy is constructed.

The invention relates to the technical field of chip packaging, in particular to a PCIe (peripheral component interface express) equipment function number border crossing prevention method supporting ARI (automatic repeat interface). The hardware layer protection process is as follows: S1-1, hot plugging; s1-2, if it is detected that the equipment declarates to support ARI, the PCIe controller hardware circuit immediately sets an equipment number register to zero; s1-3, only allowing the PCIe controller of the system to read the configuration space unidirectionally during the low level period of the reset signal PERST #; the interception process of the driving layer is as follows: S2-1, in an equipment enumeration stage, an operating system drives to dynamically read an ARI capability register; s2-2, if the equipment declarates to support ARI, forcing an equipment number register to be equal to 0, and releasing an original equipment number bit space for function number expansion; s2-3, border crossing access is blocked; and S2-4, synchronizing the state register. Compared with the prior art, correctness of device function numbers is guaranteed through two dimensions of hardware register state solidification and driver layer access truncation, and'perception-free 'fault tolerance of the PCIe device under ARI / traditional mode switching is achieved for the first time.

The invention provides a PXE network card initialization method and device compatible with 64-bit addressing and a medium, and relates to the technical field of network card initialization, and the method comprises the steps: discovering a network card device; reading a PCI configuration space of the network card equipment, obtaining information of an extended ROM base address register, and mapping a network card Option ROM to a memory shadow region; when the access of the memory mapping input and output mode fails, the initialization code performs read-write operation on the hardware register through a self-defined capability structure in a PCI configuration space of the network card equipment; based on the successfully accessed hardware register, network card hardware initialization is completed, and a PXE protocol stack structural body is established in a memory; registering system firmware as PXE starting equipment, and entering a protocol interaction stage with a PXE server; according to the invention, smooth development of a subsequent network boot flow is guaranteed, and the deployment success rate and the system stability in a large-scale batch installation scene are improved.

Embodiments of the present application provide a table entry updating method and device, electronic equipment and storage medium, and relate to the technical field of communication. The method comprises: acquiring current bandwidth occupancy of each interface every preset time length; if the current bandwidth occupancy of any interface exceeds an upper threshold or decreases to below a lower threshold, determining target bandwidth occupancy of each shortest path interface and target bandwidth occupancy of each non-shortest path interface based on the current bandwidth occupancy of each shortest path interface, the current bandwidth occupancy of each non-shortest path interface, the upper threshold and the lower threshold; calculating forwarding weight values of each shortest path interface and forwarding weight values of each non-shortest path interface based on the target bandwidth occupancy of each shortest path interface and the target bandwidth occupancy of each non-shortest path interface; and updating a forwarding bandwidth value in a hardware register table entry corresponding to each interface based on the calculated forwarding weight values. The overall bandwidth utilization can be improved.

An integrated circuit includes a memory bus coupled to a random access memory (RAM). A plurality of ports enable hardware logic to access the RAM over the memory bus. A central processing unit (CPU) is coupled to the memory bus. A first hardware logic module is coupled to a first port, of the plurality of ports, to share access to the memory bus with the CPU. A plurality of hardware registers, coupled to the plurality of ports, include a first hardware register to store a number of accesses, by the first hardware logic module, to the memory bus over the first port.

The invention discloses a dynamic link scheduling system and method among computing power cards based on multi-MCU distributed control, and belongs to the field of computers, the system comprises a plurality of computing power cards, and data physical links among the plurality of computing power cards are directly connected in a distributed manner; and the MCU is correspondingly deployed on the computing power card. Wherein an EDC is deployed on the MCU to monitor the link state of a local computing power card in real time, and a hardware register is directly controlled to execute link switching operation; the plurality of MCUs are in synchronous communication through the MACP; dLNP is deployed on the MCU, an optimal data transmission path is calculated based on the global state monitored by the EDC, and the MCU executes a data transmission path switching instruction. According to the scheme, the control right is released to the edge of each computing power card from the central CPU, that is, link scheduling control is stripped from the CPU to the distributed MCUs, the MCUs guide data transmission paths only by sending lightweight control commands, data streams are not directly processed, control functions are deployed on each acceleration card in a distributed mode, and finally the effects of low delay and the like of data links between the computing power cards are achieved.

The invention discloses a memory bank fault analysis method, device and equipment and a storage medium, and relates to the technical field of server security management and control, the method comprises the following steps: reading an internal error state register of target memory equipment according to a preset monitoring period to obtain real-time error information; and performing fault prediction analysis based on the real-time error information to obtain a memory pre-fault judgment result corresponding to the target memory device. According to the method and the device, the internal hardware register is directly read to obtain the real-time error information, and the pre-fault state of the target memory equipment is accurately identified based on the real-time error information, so that the influence of a shielding effect of an on-chip error correction code on fault analysis can be avoided, and the accuracy and the reliability of fault prediction are improved. Therefore, the fault of the DDR5 memory bank can be recognized in advance by directly utilizing the data of the hardware register, and fault prediction of the DDR5 memory bank is realized.

The invention particularly relates to a cluster error code correction parameter learning method and system, and relates to the technical field of distributed cluster communication and error code correction. A dynamic neighborhood topology construction module; a local transfer rule engine module; an asynchronous random updating engine module; and an entropy monitoring and stability detection module. According to the method, cellular neighbors are defined according to physical and logic two dimensions, and cluster dynamic changes such as node online and offline, link faults and replica migration are accurately adapted; and physical parameter microsecond acquisition is realized through direct reading of a hardware register, communication and calculation overhead is greatly reduced through discrete coding and lightweight custom messages, and the core requirement of lightweight interaction of the cluster is met.

The described apparatus and methods relate to memory flow control registers for memory systems that can support non-deterministic protocols. To help manage the flow of memory requests in a system, a memory device can include logic, such as a hardware register, that can store a value indicating a total number of memory requests that can be serviced by the memory device simultaneously. The logic can be configured by a device manufacturer during assembly. The manufacturer can determine limits or capabilities of the system based on components and structure, and disclose the capabilities, including QoS, based on the limits. When the memory device is connected to a host, the host can read the value and limit the number of memory requests sent to the device based on the value. Thus, the memory flow control register can improve latency and bandwidth when accessing a memory device via an interconnect.

The application provides a PXE network card initialization method, device and medium compatible with 64-bit addressing, relates to the technical field of network card initialization, and comprises the following steps: discovering a network card device; reading the PCI configuration space of the network card device, acquiring extended ROM base address register information, and mapping the network card Option ROM to a memory shadow area; when memory mapping input / output mode access fails, the initialization code performs read / write operation on the hardware register through a self-defined capability structure in the PCI configuration space of the network card device; based on the successfully accessed hardware register, network card hardware initialization is completed, and a PXE protocol stack structure body is established in the memory; the system firmware is registered as a PXE starting device, and a protocol interaction stage with a PXE server is entered; and the application guarantees the smooth development of a subsequent network booting process, and improves the deployment success rate and system stability in a large-scale batch deployment environment.

This invention discloses a design method for a RISC-V AIA interrupt-configurable multi-privilege-level IMSIC controller, comprising: setting a programmable configuration register MS_CUT_CFG in the IMSIC to dynamically allocate interrupt file resources for machine mode (M-mode) and supervisor mode (S-mode) at runtime; controlling the allocation ratio of the actual physical storage space of interrupt files in machine mode (M-mode) and supervisor mode (S-mode) through the configuration register MS_CUT_CFG to achieve dynamic reuse of interrupt file resources; physically sharing the same hardware register array for the interrupt enable register group (IE) and interrupt suspend register group (IP) of machine mode (M-mode) and supervisor mode (S-mode); and mapping suspended but executable interrupt requests to the corresponding privilege level and submitting them to the processor core through an interrupt arbitration circuit based on the current value of the configuration register. This invention overcomes the limitations of the static resource configuration strategy for IMSIC interrupt files, significantly enhancing the flexibility and dynamic scenario adaptability of RISC-V AIA interrupt applications.

This invention discloses a magnetic resonance imaging (MRI) sequence translation communication control system and method. The system includes: a parameter customization module for receiving and verifying user-configured MRI parameters; a sequence generation module for generating MRI sequence files conforming to the Pulseq standard based on the verified parameters; a sequence translation module for translating the MRI sequence files into a TLV format hardware instruction stream according to the target spectrometer hardware configuration file; a hardware control module for writing the TLV instruction stream into the spectrometer hardware registers via an open hardware instruction bus, controlling the spectrometer to transmit radio frequency pulses, apply gradient fields, and acquire MRI signals; and a verification and feedback module for real-time monitoring of hardware execution status and data consistency verification. This invention solves the problems of complex hardware interfaces and poor sequence portability in existing MRI systems by constructing a closed-loop architecture of "parameter configuration - sequence generation - TLV translation - hardware execution," thereby improving the system's versatility, scalability, and control accuracy.

This application discloses a method, apparatus, device, and storage medium for initializing a single-write register in an embedded system, relating to the field of system startup control technology. The method includes: responding to a startup signal of the embedded system, running a bootloader and performing basic system initialization; after basic system initialization, checking whether the jump condition to the main application is met; when the jump condition is met, performing a jump operation from the bootloader to the main application; and after successfully jumping to the main application, executing the system initialization function of the main application to complete the initialization of hardware registers with single-write constraints. This application can improve the stability of system startup.

The invention provides a high-reliability dynamic self-adaptive satellite data receiving and processing method. The method comprises the steps of setting a reference timestamp, establishing a data segment receiving mechanism, emptying a buffer area and a counter, dynamically receiving satellite data, analyzing the data, dynamically emptying a hardware register, establishing a data mapping matrix and establishing a bus data integrity checking process. According to the invention, through satellite data dynamic receiving, an originally concentrated satellite data receiving process is dispersed, and the problem of time slice congestion of a civil aircraft real-time navigation system is solved; the visibility of the satellite data state is ensured through data analysis; by dynamically emptying the register, the real-time system idle time slice is effectively utilized to ensure the robustness of the system; by establishing a data mapping matrix, rapid positioning of data receiving information and data state information is supported; and establishing a bus data integrity checking process to ensure the reliability of the received satellite data.

The invention discloses a serial communication method and an electronic device, and relates to the technical field of I2C communication, and the method comprises the steps: generating a plurality of operation data packets based on a serial communication task message, reading each operation data packet according to the execution time sequence of each operation step corresponding to the plurality of operation data packets, a hardware register is configured according to the operation information corresponding to the read operation data packet, so that the external equipment reads the operation information from the hardware register through the serial communication bus and executes corresponding operation, and the processor jumps out of the current operation after completing the configuration of the hardware register. And after the external equipment is detected to execute the corresponding operation based on the operation information, continuing to read the next operation data packet until the plurality of operation data packets are all processed, and completing a serial communication process, so that waiting for the end of the whole serial communication process is not needed, and the communication efficiency is improved. Wait waste time introduced when the processor waits for the external equipment to execute the operation is fully utilized, and the restriction of serial communication on the read-write performance of the hard disk is effectively relieved.

Systems and methods are provided to reduce the latency in accessing an input / output (I / O) hardware register by software executing on a central processing unit (CPU). The hardware register is located in a controller coupled to the CPU via an I / O bus. The CPU software can send a command to the controller for execution. The controller can execute the command and update the hardware register to indicate that the command has been executed. The controller can write contents of the hardware register to a specified address in a CPU memory that is assigned by the CPU software. The CPU software can read the specified address to determine that the command has been executed instead of reading the hardware register on the I / O bus.

The invention discloses an RS232 port multi-device control system based on serial port baud rate dynamic switching, two-way communication is established through an RS232 port and a plurality of external devices, a software control module dynamically adjusts communication parameters of the port to adapt to different device requirements, and an external storage medium stores the communication parameters of the devices; an equipment identification unit in the software control module is matched with an identifier of equipment to be communicated, a parameter switching unit configures a port hardware register to switch the baud rate according to the identifier, and a control code processing unit generates and sends a control code and receives feedback data returned by the equipment at the same time. The system effectively solves three major problems of poor stability, low resource utilization rate and insufficient expansibility in traditional RS232 multi-device communication through dynamic parameter adaptation and a device scheduling mechanism. And the integration efficiency and reliability under industrial and Internet of Things scenes are remarkably improved.

This disclosure provides a fault diagnosis method and apparatus, applicable to the field of computer fault diagnosis technology. The fault diagnosis method includes: determining the physical status information and first asset information of the target hard disk through an out-of-band management channel; determining the logical status information and second asset information of the target hard disk through a power-on initialized in-band management channel; obtaining connection status information indicating the physical connection status of the target hard disk from a hardware register; obtaining a verification result based on at least two of the physical status information, first asset information, logical status information, second asset information, and connection status information; and determining the fault type associated with the target hard disk based on the verification result.

The invention discloses a Direct3D 12 derivative calculation implementation method based on hardware-assisted sampling, which comprises the following steps of: when a GPU (Graphics Processing Unit) does not support VKKHRComputeshaders, establishing an association table of a texture sampler, a derivative function parameter and a sampling context by creating a calculation shader, marking Quads or a Linear execution mode by VKD3D, rewriting a D3D12 derivative function by using a constructed SPIR-V instruction sequence to obtain a Vulkan shader module, splitting a working group dimension, and obtaining a Vulkan shader module; constructing a Vulkan pipeline layout and binding the Vulkan pipeline layout to a command buffer area, replacing a native sampling function with a sampling proxy function when a texture sampling command is recorded, calculating a derivative by the GPU after the command buffer area is submitted, calculating an LOD value by the sampling proxy function, writing the LOD value into a Vulkan push constant and a GPU sampling unit hardware register, and resubmitting the Vulkan pipeline layout to a GPU queue to complete rendering.

The present application relates to the technical field of artificial intelligence computing power scheduling, in particular to a load balancing and performance guarantee method for multi-modal AI computing power service, comprising: firstly, analyzing request characteristics, extracting a computing work set and a minimum safe capacity to generate a local key-value cache baseline, and fitting to generate a minimal algebraic arrival curve of network direct writing traffic; then, combining the baseline, the curve and the network topology routing hop count to build a key-value cache non-eviction model and solve the physical cache capacity limit; further, determining the number of isolated paths according to the limit and the single-path capacity, calling the hardware register to set the capacity bitmask, and building a space-time physical isolation architecture; finally, when the traffic breaks through the upper bound of the curve, establishing an orthogonal damping constraint relationship based on equivalent arithmetic strength, and synchronously reducing the computing end micro-batch and the network end transmission unit. The present application solves the problem of physical squeezing of local cache by network direct writing through bottom-layer physical isolation and double-end orthogonal feedback.

Systems and techniques are described herein for offloading cryptographic services. For example, a method may include receiving a request to provide a cryptographic service type and initiating a cryptographic algorithm in a cryptographic hardware component, where the cryptographic algorithm is associated with the cryptographic service type. The method may further include applying a cryptographic operation to data to obtain a cryptographic result. The cryptographic operation is associated with the cryptographic algorithm. The method may further include storing at least a portion of the cryptographic result in a hardware register of the cryptographic hardware component. The cryptographic result is configured for use for performing a cryptographic action.

Embodiments of a system, method and apparatus are described for reducing power consumption of a battery-powered electronic device. A hardware polling peripheral operates in conjunction with a CPU within the batten -powered electronic device. When the CPU enters a quiescent state in order to save power, the hardware polling peripheral begins the polling cycle that polls one or more I / O pins of the hardware polling peripheral to detect a change in state. Polling is controlled by hardware registers and digital logic circuits without the use of firmware. When the hardware polling peripheral determines that an I / O pin has changed state, it wakes the CPU from the quiescent state via an interrupt.

Provided is a method for configuring an electronic system for a secure execution of a code comprising a plurality of functions. The electronic system is configured for applying during an execution of a function a security countermeasure configuration among a plurality of security countermeasure configurations. The method is performed by said electronic system comprising a hardware processor, security hardware registers configured for storing start addresses of functions among said plurality of functions and associated security countermeasure configurations to be applied during an execution of said functions. A detection system is configured to detect an attack on said electronic system during an execution of a function among said plurality of functions.

A method includes storing, by a processing device of a memory sub-system controller, on a first memory device, a first address translation metadata structure. An instruction reflecting a namespace change associated with a zoned namespace is received and the first address translation metadata structure is updated based on the instruction. An address translation metadata pointer to reference the first address translation metadata structure during address translation operations associated with the plurality of zoned namespaces is updated and the first address translation metadata structure is copied into a second memory device, thus creating a second address translation metadata structure. The hardware register is updated to point to the second address translation metadata structure during address translation operations associated with the plurality of zoned namespaces.

The application discloses a kind of Direct3D 12 derivative calculation implementation methods based on hardware auxiliary sampling, when GPU does not support VK_KHR_compute_shader_derivatives, application creates calculation shader, VKD3D mark Quads or Linear execution mode establishes the association table of texture sampler, derivative function parameter and sampling context, to construct SPIR-V instruction sequence, rewrite D3D12 derivative function and obtain Vulkan shader module, split workgroup dimension, construct Vulkan pipeline layout and bind to command buffer, when recording texture sampling command, replace native sampling function with sampling proxy function, after submitting command buffer, GPU calculates derivative, sampling proxy function calculates LOD value and writes Vulkan push constant and GPU sampling unit hardware register, re-submits to GPU queue and completes rendering.

The invention discloses a fault positioning method, a solid state disk and a storage medium, and the method comprises the steps: in the process that the solid state disk runs a firmware code, when it is determined that a code at a target position in the firmware code is executed according to a tracking mark, generating and storing corresponding tracking log data; the tracking mark is inserted into the target position in the firmware code in advance in a compiling stage; the target position comprises an inlet and an outlet of a target function and an operation inlet and an operation outlet of target hardware; after monitoring that a fault occurs, determining abnormal log data from the tracking log data, and storing hardware register data associated with the abnormal log data; and carrying out fault positioning according to the tracking log data and the hardware register data. According to the scheme, debugging is carried out without manually setting breakpoints so as to carry out fault positioning, so that the fault positioning efficiency can be greatly improved, and the research and development debugging cost can be reduced.

This invention specifically relates to a cluster error correction parameter learning method and system, encompassing the fields of distributed cluster communication and error correction technology. It includes: a cell state space definition module; a dynamic neighborhood topology construction module; a local transition rule engine module; an asynchronous random update engine module; and an entropy monitoring and stability detection module. In this invention, cell neighbors are defined along both physical and logical dimensions to accurately adapt to dynamic cluster changes such as node online / offline status, link failures, and replica migration. Furthermore, direct reading from hardware registers enables microsecond-level acquisition of physical parameters. Discretized encoding and lightweight custom messages significantly reduce communication and computational overhead, meeting the core requirement of lightweight cluster interaction.

The application discloses an endoscope image self-adaptive enhancement method and system based on NPU, and the method comprises the following steps: performing basic processing operation on original image data output by an image sensor through an ISP to generate an image frame in a standard format; loading a lightweight semantic segmentation model through an NPU to perform real-time inference on the image frame, acquire a pixel-level segmentation mask, and perform quantitative analysis on the pixel-level segmentation mask to output diagnosis data; generating a control parameter set based on the diagnosis data and a preset mapping strategy; and delivering the control parameter set to a hardware register or a driving layer corresponding to the ISP through a control interface of a V4L2 subsystem in real time to dynamically adjust a subsequent processing process of the image frame. The application realizes dynamic and accurate regulation and control of ISP parameters, significantly improves the image quality optimization effect of an endoscope image while maintaining the low-cost and low-power consumption advantages of a full SoC scheme, and meets the clinical diagnosis requirements.

The invention relates to the technical field of spaceflight electronics, in particular to an FPGA hardware acceleration adaptive data distribution method and device based on multi-dimensional state awareness and a storage medium, and the method comprises the following steps: S1, directly sampling four-dimensional state parameters of each SATA channel through a hardware register; s2, a lookup table is used for replacing a hardware calculation engine of a multiplier to fuse and calculate the parameters, and a dynamic weight coefficient is generated; s3, based on the weight coefficient, adaptively distributing the input data flow to each SATA channel through a two-stage distribution mechanism; and S4, dynamically correcting the evaluation parameters through closed-loop feedback, and starting a progressive degradation strategy when the channel is abnormal. The method is completely implemented on the FPGA hardware level, the problem that a traditional static strategy cannot adapt to SSD real-time performance fluctuation is solved, lossless and low-delay disk dropping of 10G Ethernet full-speed data is achieved, and the method has the advantages of being high in reliability and long in service life.

The invention relates to a memory bank operation acceleration device and method for chip debugging, which improve the existing chip debugging operation by starting from the reality of the memory read-write operation of the existing chip, and add three hardware registers (RWMCR, FWACR and WCCR) in an ET component, so as to greatly reduce the repeated address writing operation in the read-write operation, and improve the chip debugging speed. According to the method, the data volume of the address and the data volume of the operation in the memory bank operation command are greatly reduced, and when the test program is large enough, the data volume sending can be reduced by about 50%, so that the memory read-write operation efficiency of the memory bank is greatly improved, and the purpose of greatly improving the test efficiency of a chip is achieved.