66 results about "Hardware register" patented technology

The invention relates to the field of digital power supply control, and provides a parameterized digital control method and system suitable for a wide power range charging module, and the method comprises the steps: collecting an original sensor signal, constructing a slow working condition feature vector through adaptive-temperature drift compensation, and driving a physical constraint reference prediction model to generate a second baseline behavior parameter vector; monitoring a gate driving current by using a gate-drain capacitor, extracting a transient characteristic value, and quantifying the transient characteristic value into a ZVS quality factor; the slow working condition feature vector and the ZVS quality factor are fused, a correction vector is generated through an adaptive prediction model, a control parameter vector is generated in combination with a second baseline behavior parameter vector, and online updating is carried out according to feedback; executing hardware physical limit constraint according to the security constraint set, generating security parameters and abnormal flag bits, and writing the security parameters and the abnormal flag bits into a hardware register in a fixed-point manner after cooperating with ZVS quality factor arbitration. According to the method, physical constraint prediction and transient perception correction are fused, and a digital control system considering dynamic response, drift compensation and safety redundancy is constructed.

The invention relates to the technical field of chip packaging, in particular to a PCIe (peripheral component interface express) equipment function number border crossing prevention method supporting ARI (automatic repeat interface). The hardware layer protection process is as follows: S1-1, hot plugging; s1-2, if it is detected that the equipment declarates to support ARI, the PCIe controller hardware circuit immediately sets an equipment number register to zero; s1-3, only allowing the PCIe controller of the system to read the configuration space unidirectionally during the low level period of the reset signal PERST #; the interception process of the driving layer is as follows: S2-1, in an equipment enumeration stage, an operating system drives to dynamically read an ARI capability register; s2-2, if the equipment declarates to support ARI, forcing an equipment number register to be equal to 0, and releasing an original equipment number bit space for function number expansion; s2-3, border crossing access is blocked; and S2-4, synchronizing the state register. Compared with the prior art, correctness of device function numbers is guaranteed through two dimensions of hardware register state solidification and driver layer access truncation, and'perception-free 'fault tolerance of the PCIe device under ARI / traditional mode switching is achieved for the first time.

The invention discloses a bandwidth determination method and device for a host channel adapter, and relates to the field of computers.The bandwidth determination method comprises the steps that a preset interface of an operating system is adopted to drive and directly access a hardware register of the host channel adapter through the host channel adapter, and data invisibility of an operating system layer in a remote direct memory access framework is penetrated; original values of a receiving byte counter and a sending byte counter maintained by firmware in a hardware register are accurately captured, and the byte increment change is dynamically calculated in combination with a preset time interval, so that the aim of millisecond-level real-time monitoring on the network traffic is fulfilled on the premise of not modifying a kernel and not intercepting a data packet; therefore, the technical effects of high-precision bandwidth measurement, ultra-low performance overhead, full-flow penetration capability and cross-platform expandability are realized, and the fault diagnosis and performance tuning efficiency of the distributed system is remarkably improved.

The invention provides a PXE network card initialization method and device compatible with 64-bit addressing and a medium, and relates to the technical field of network card initialization, and the method comprises the steps: discovering a network card device; reading a PCI configuration space of the network card equipment, obtaining information of an extended ROM base address register, and mapping a network card Option ROM to a memory shadow region; when the access of the memory mapping input and output mode fails, the initialization code performs read-write operation on the hardware register through a self-defined capability structure in a PCI configuration space of the network card equipment; based on the successfully accessed hardware register, network card hardware initialization is completed, and a PXE protocol stack structural body is established in a memory; registering system firmware as PXE starting equipment, and entering a protocol interaction stage with a PXE server; according to the invention, smooth development of a subsequent network boot flow is guaranteed, and the deployment success rate and the system stability in a large-scale batch installation scene are improved.

The invention provides a data encryption method of a storage device, a data transmission method and an electronic device, and belongs to the technical field of storage. The data encryption method of the storage equipment comprises the following steps: determining the row number and the column number of a key matrix according to the specification of a key stored in a hardware register in the storage equipment, and taking a unit matrix with the determined row number and the determined column number as an initial key matrix; arranging a plurality of digits out of order to form an interchange array, and limiting the column number position of an element I in the initial key matrix by the digits in the interchange array to form an intermediate key matrix; performing multiplied elementary row transformation on each row of the intermediate key matrix to obtain a target key matrix, and obtaining a target decryption matrix corresponding to the target key matrix; and encrypting plaintext data by using the target key matrix to form a ciphertext matrix. By means of the data encryption method of the storage device, a concise and safe data encryption method can be provided for a user.

Systems and methods include an Information Handling System (IHS) that is adapted to manage the operation of sensors that are coupled to the IHS. An Embedded Controller (EC) of the IHS receives a sensor configuration request and identifies one or more sensors of the IHS that are to be configured based on the request. The EC identifies an interface for accessing each of these sensors, where interface may be managed directly by the EC or may be managed by another hardware component of the IHS. The EC identifies one or more hardware registers for configuring each respective sensor. Via the identified interface, the EC modifies the identified hardware registers for each of the sensors in order to fulfill the sensor configuration request.

The invention discloses a cache division method, system and device and a storage medium. The method comprises the following steps: analyzing a device tree to obtain hardware resource information; creating a plurality of address space domains based on the hardware resource information, and configuring a hardware register; dynamically dividing the cache size of each address space domain based on a received re-division instruction according to the hardware register; the redivision instruction is issued by the address space domain. According to the method, dynamic division of the cache resources is realized through the re-division instruction of the address space domain, and the cache division efficiency and flexibility can be improved. The method can be widely applied to the technical field of computers.

The present invention discloses a method, apparatus, device, medium and product for accelerating the multiplication of double sparse matrices. The method includes: locating a set of compressed matrices matching a first sparse matrix and a second sparse matrix in the global memory of a computing chip according to the sparse matrix multiplication requirement; sequentially transferring the set of compressed matrices and the second sparse matrix from the global memory to the hardware registers of the computing chip in the form of data blocks; and gradually calculating the multiplication result of the first sparse matrix and the second sparse matrix by a sparse computing unit of the computing chip according to the data loaded in batches in the hardware registers. The technical solution of the embodiments of the present invention can give full play to the hardware acceleration performance of the sparse computing unit in the computing chip, and thus greatly optimize the overhead of computing, bandwidth and storage resources in the process of multiplying double sparse matrices, and is particularly applicable to the model calculation scenario of a mixture-of-experts model.

Embodiments of the present application provide a table entry updating method and device, electronic equipment and storage medium, and relate to the technical field of communication. The method comprises: acquiring current bandwidth occupancy of each interface every preset time length; if the current bandwidth occupancy of any interface exceeds an upper threshold or decreases to below a lower threshold, determining target bandwidth occupancy of each shortest path interface and target bandwidth occupancy of each non-shortest path interface based on the current bandwidth occupancy of each shortest path interface, the current bandwidth occupancy of each non-shortest path interface, the upper threshold and the lower threshold; calculating forwarding weight values of each shortest path interface and forwarding weight values of each non-shortest path interface based on the target bandwidth occupancy of each shortest path interface and the target bandwidth occupancy of each non-shortest path interface; and updating a forwarding bandwidth value in a hardware register table entry corresponding to each interface based on the calculated forwarding weight values. The overall bandwidth utilization can be improved.

The invention discloses a GPIO (General Purpose Input / Output) function parameter configuration method and system and a storage medium, and the method comprises the steps: receiving a configuration instruction input by a user through a configuration interface of a user configuration layer, and generating structured configuration data corresponding to a GPIO function according to the configuration instruction; persistently storing the structured configuration data by a persistence layer through a nonvolatile memory to obtain persistent configuration data; and when the system is restarted, loading the persistent configuration data through a kernel loading layer driver, and writing the persistent configuration data into a hardware register of a GPIO (General Purpose Input / Output) controller. The technical effect of'one-time configuration and permanent effectiveness' is achieved, the configuration process of GPIO is converted into simple, automatic and reliable software-level operation from professional and manual hardware-level operation, and finally the technical purposes of improving development efficiency, reducing production cost and enhancing system reliability are achieved.

Systems and techniques are provided for wireless communications. For example, a network device can receive information indicative of a first carrier aggregation (CA) configuration including a primary component carrier (PCC) and a set of secondary component carriers (SCCs). A predicted updated CA configuration can be generated to include a predicted PCC or a predicted SCC, based on measurements of a particular neighboring cell. A plurality of hardware register values can be determined for implementing an RF chain corresponding to the predicted updated CA configuration, based on the measurements of the particular neighboring cell. The network device can receive information indicative of an updated C A configuration different from the first C A configuration and including at least one of the predicted PCC or the predicted SCC. The network device can perform C A tuning using the plurality of hardware register values of the RF hardware register configuration.

In an example, a bootlog associated with a boot of the controller is accessed from the non-volatile memory of the controller, and a first digest of the bootlog is computed. A second digest of the bootlog is stored in a read-only hardware register in the non-volatile memory and subsequently extracted. The first and second digests are compared to determine if the controller is compromised. The controller is considered compromised when the digests do not match, and the bootlog is considered legitimate when the digests match.

An integrated circuit includes a memory bus coupled to a random access memory (RAM). A plurality of ports enable hardware logic to access the RAM over the memory bus. A central processing unit (CPU) is coupled to the memory bus. A first hardware logic module is coupled to a first port, of the plurality of ports, to share access to the memory bus with the CPU. A plurality of hardware registers, coupled to the plurality of ports, include a first hardware register to store a number of accesses, by the first hardware logic module, to the memory bus over the first port.

The invention discloses a dynamic link scheduling system and method among computing power cards based on multi-MCU distributed control, and belongs to the field of computers, the system comprises a plurality of computing power cards, and data physical links among the plurality of computing power cards are directly connected in a distributed manner; and the MCU is correspondingly deployed on the computing power card. Wherein an EDC is deployed on the MCU to monitor the link state of a local computing power card in real time, and a hardware register is directly controlled to execute link switching operation; the plurality of MCUs are in synchronous communication through the MACP; dLNP is deployed on the MCU, an optimal data transmission path is calculated based on the global state monitored by the EDC, and the MCU executes a data transmission path switching instruction. According to the scheme, the control right is released to the edge of each computing power card from the central CPU, that is, link scheduling control is stripped from the CPU to the distributed MCUs, the MCUs guide data transmission paths only by sending lightweight control commands, data streams are not directly processed, control functions are deployed on each acceleration card in a distributed mode, and finally the effects of low delay and the like of data links between the computing power cards are achieved.

The invention discloses a memory bank fault analysis method, device and equipment and a storage medium, and relates to the technical field of server security management and control, the method comprises the following steps: reading an internal error state register of target memory equipment according to a preset monitoring period to obtain real-time error information; and performing fault prediction analysis based on the real-time error information to obtain a memory pre-fault judgment result corresponding to the target memory device. According to the method and the device, the internal hardware register is directly read to obtain the real-time error information, and the pre-fault state of the target memory equipment is accurately identified based on the real-time error information, so that the influence of a shielding effect of an on-chip error correction code on fault analysis can be avoided, and the accuracy and the reliability of fault prediction are improved. Therefore, the fault of the DDR5 memory bank can be recognized in advance by directly utilizing the data of the hardware register, and fault prediction of the DDR5 memory bank is realized.

The invention particularly relates to a cluster error code correction parameter learning method and system, and relates to the technical field of distributed cluster communication and error code correction. A dynamic neighborhood topology construction module; a local transfer rule engine module; an asynchronous random updating engine module; and an entropy monitoring and stability detection module. According to the method, cellular neighbors are defined according to physical and logic two dimensions, and cluster dynamic changes such as node online and offline, link faults and replica migration are accurately adapted; and physical parameter microsecond acquisition is realized through direct reading of a hardware register, communication and calculation overhead is greatly reduced through discrete coding and lightweight custom messages, and the core requirement of lightweight interaction of the cluster is met.

The invention discloses a software and hardware collaboration method for MCU verification. The software and hardware collaboration method comprises the following steps: S1, respectively mapping each pin which needs to be controlled during MCU verification to each corresponding hole address; respectively defining each register type variable pointing to each hole address; and S2, MCU verification is started, hardware monitoring is carried out on each operation of the MCU, when a specific operation corresponding to any pin is identified, data or an instruction corresponding to the specific operation is stored in the corresponding hole address through the corresponding register type variable, and verification is completed according to the stored data or instruction. According to the method, the pins needing to be verified and the hole addresses in the hardware register are subjected to one-to-one mapping, so that MCU verification can be directly completed only through a software level, operation contents such as force commands and delay information increase are reduced, the verification efficiency is greatly improved, and the verification time is saved.

The present invention provides a data encryption method, a data transmission method, and an electronic device for a storage device, belonging to the field of storage technology. The data encryption method for the storage device includes the following steps: determining the number of rows and columns of a key matrix based on the specifications of the hardware register storing the key in the storage device, and using a unit matrix with the determined number of rows and columns as the initial key matrix; arranging multiple numbers in random order to form an interchange array, and using the numbers in the interchange array to define the column position of element one in the initial key matrix to form an intermediate key matrix; performing a doubling elementary row transformation on each row of the intermediate key matrix to obtain a target key matrix, and obtaining a target decryption matrix corresponding to the target key matrix; and encrypting plaintext data using the target key matrix to form a ciphertext matrix. The data encryption method for a storage device provided by the present invention can provide users with a simple and secure data encryption method.

The described apparatus and methods relate to memory flow control registers for memory systems that can support non-deterministic protocols. To help manage the flow of memory requests in a system, a memory device can include logic, such as a hardware register, that can store a value indicating a total number of memory requests that can be serviced by the memory device simultaneously. The logic can be configured by a device manufacturer during assembly. The manufacturer can determine limits or capabilities of the system based on components and structure, and disclose the capabilities, including QoS, based on the limits. When the memory device is connected to a host, the host can read the value and limit the number of memory requests sent to the device based on the value. Thus, the memory flow control register can improve latency and bandwidth when accessing a memory device via an interconnect.

The application provides a PXE network card initialization method, device and medium compatible with 64-bit addressing, relates to the technical field of network card initialization, and comprises the following steps: discovering a network card device; reading the PCI configuration space of the network card device, acquiring extended ROM base address register information, and mapping the network card Option ROM to a memory shadow area; when memory mapping input / output mode access fails, the initialization code performs read / write operation on the hardware register through a self-defined capability structure in the PCI configuration space of the network card device; based on the successfully accessed hardware register, network card hardware initialization is completed, and a PXE protocol stack structure body is established in the memory; the system firmware is registered as a PXE starting device, and a protocol interaction stage with a PXE server is entered; and the application guarantees the smooth development of a subsequent network booting process, and improves the deployment success rate and system stability in a large-scale batch deployment environment.

This invention discloses a design method for a RISC-V AIA interrupt-configurable multi-privilege-level IMSIC controller, comprising: setting a programmable configuration register MS_CUT_CFG in the IMSIC to dynamically allocate interrupt file resources for machine mode (M-mode) and supervisor mode (S-mode) at runtime; controlling the allocation ratio of the actual physical storage space of interrupt files in machine mode (M-mode) and supervisor mode (S-mode) through the configuration register MS_CUT_CFG to achieve dynamic reuse of interrupt file resources; physically sharing the same hardware register array for the interrupt enable register group (IE) and interrupt suspend register group (IP) of machine mode (M-mode) and supervisor mode (S-mode); and mapping suspended but executable interrupt requests to the corresponding privilege level and submitting them to the processor core through an interrupt arbitration circuit based on the current value of the configuration register. This invention overcomes the limitations of the static resource configuration strategy for IMSIC interrupt files, significantly enhancing the flexibility and dynamic scenario adaptability of RISC-V AIA interrupt applications.

This invention discloses a magnetic resonance imaging (MRI) sequence translation communication control system and method. The system includes: a parameter customization module for receiving and verifying user-configured MRI parameters; a sequence generation module for generating MRI sequence files conforming to the Pulseq standard based on the verified parameters; a sequence translation module for translating the MRI sequence files into a TLV format hardware instruction stream according to the target spectrometer hardware configuration file; a hardware control module for writing the TLV instruction stream into the spectrometer hardware registers via an open hardware instruction bus, controlling the spectrometer to transmit radio frequency pulses, apply gradient fields, and acquire MRI signals; and a verification and feedback module for real-time monitoring of hardware execution status and data consistency verification. This invention solves the problems of complex hardware interfaces and poor sequence portability in existing MRI systems by constructing a closed-loop architecture of "parameter configuration - sequence generation - TLV translation - hardware execution," thereby improving the system's versatility, scalability, and control accuracy.

This application discloses a method, apparatus, device, and storage medium for initializing a single-write register in an embedded system, relating to the field of system startup control technology. The method includes: responding to a startup signal of the embedded system, running a bootloader and performing basic system initialization; after basic system initialization, checking whether the jump condition to the main application is met; when the jump condition is met, performing a jump operation from the bootloader to the main application; and after successfully jumping to the main application, executing the system initialization function of the main application to complete the initialization of hardware registers with single-write constraints. This application can improve the stability of system startup.

The present application discloses a bandwidth determination method and apparatus for a host channel adapter, which relates to the field of computers. The method comprises: using a preset interface of an operating system to directly access the hardware registers of a host channel adapter via a host channel adapter driver, thereby penetrating the data invisibility of the operating system layer in a remote direct memory access architecture. Furthermore, by accurately capturing the original values ​​of a receive byte counter and a send byte counter maintained by firmware in the hardware registers, and dynamically calculating byte increments based on preset time intervals, the method achieves the purpose of millisecond-level real-time monitoring of network traffic without requiring kernel modifications or intercepting data packets. This method thus realizes the technical effects of high-precision bandwidth measurement, ultra-low performance overhead, full traffic penetration capability, and cross-platform scalability, significantly improving the efficiency of fault diagnosis and performance tuning of distributed systems.

The invention provides a high-reliability dynamic self-adaptive satellite data receiving and processing method. The method comprises the steps of setting a reference timestamp, establishing a data segment receiving mechanism, emptying a buffer area and a counter, dynamically receiving satellite data, analyzing the data, dynamically emptying a hardware register, establishing a data mapping matrix and establishing a bus data integrity checking process. According to the invention, through satellite data dynamic receiving, an originally concentrated satellite data receiving process is dispersed, and the problem of time slice congestion of a civil aircraft real-time navigation system is solved; the visibility of the satellite data state is ensured through data analysis; by dynamically emptying the register, the real-time system idle time slice is effectively utilized to ensure the robustness of the system; by establishing a data mapping matrix, rapid positioning of data receiving information and data state information is supported; and establishing a bus data integrity checking process to ensure the reliability of the received satellite data.

The invention discloses an exception detection method, system and device and a storage medium, relates to the technical field of data processing, and is used for determining an exception root by comparing data of different levels in a server system so as to improve the accuracy of exception detection. The method comprises the following steps: collecting hardware register data and BMC interface layer data of each component in a server system; establishing a mapping relation between the hardware register data and the BMC interface layer data; the hardware register data and the BMC interface layer data which have the mapping relation are compared, and the cause of the abnormity is determined according to the comparison result.

The invention discloses an anti-theft verification method and system, and relates to the technical field of information security, a linked protection system is formed through three-level cooperative verification of a driving layer, a system layer and an application layer, and in the driving layer, an identification interface with read-only attributes is strongly coupled with hardware peripherals, so that the security of the system is improved. A unique identification code is generated through hard coding of a hardware register address, mirror image transplantation is blocked from a bottom layer, a hidden self-starting service of a system layer is operated preferentially at the initial stage of equipment starting, an unauthorized device cannot load a system function by detecting existence of an interface and legality of the identification code, and an application layer performs secondary verification before a core function is called. The sensitive operation is forbidden, the multi-level verification mechanism enables an attacker to simultaneously break through three levels of hardware binding, system startup protection and application function limitation, full-link security protection for preventing extraction, startup and use is constructed, and the uniqueness of the system and the application is effectively guaranteed.

The invention discloses a serial communication method and an electronic device, and relates to the technical field of I2C communication, and the method comprises the steps: generating a plurality of operation data packets based on a serial communication task message, reading each operation data packet according to the execution time sequence of each operation step corresponding to the plurality of operation data packets, a hardware register is configured according to the operation information corresponding to the read operation data packet, so that the external equipment reads the operation information from the hardware register through the serial communication bus and executes corresponding operation, and the processor jumps out of the current operation after completing the configuration of the hardware register. And after the external equipment is detected to execute the corresponding operation based on the operation information, continuing to read the next operation data packet until the plurality of operation data packets are all processed, and completing a serial communication process, so that waiting for the end of the whole serial communication process is not needed, and the communication efficiency is improved. Wait waste time introduced when the processor waits for the external equipment to execute the operation is fully utilized, and the restriction of serial communication on the read-write performance of the hard disk is effectively relieved.

Systems and methods are provided to reduce the latency in accessing an input / output (I / O) hardware register by software executing on a central processing unit (CPU). The hardware register is located in a controller coupled to the CPU via an I / O bus. The CPU software can send a command to the controller for execution. The controller can execute the command and update the hardware register to indicate that the command has been executed. The controller can write contents of the hardware register to a specified address in a CPU memory that is assigned by the CPU software. The CPU software can read the specified address to determine that the command has been executed instead of reading the hardware register on the I / O bus.

The invention relates to the technical field of computers, in particular to a live migration method and device of virtual equipment, electronic equipment and a storage medium. According to the embodiment of the invention, by dynamically adjusting the snapshot interval and monitoring the bit error rate, the problem of the existing KVM thermal migration scheme is effectively solved. On one hand, the dirty page rate of the memory of the virtual device is obtained in real time, the Ceph snapshot interval is shortened when the dirty page rate exceeds the threshold value, and compared with a long interval which is fixed to be larger than or equal to 500 ms, the state can be recorded in time when the service state changes rapidly, loss of service data such as pictures is reduced, and user experience is guaranteed. On the other hand, software simulation link monitoring is abandoned, the bit error rate is monitored in a physical layer hardware register reading mode, misinformation generated by network fluctuation is reduced, a large amount of unnecessary migration is avoided, system resource overhead is reduced, service interruption caused by migrating is prevented, system stability and reliability are improved, and service continuity in cloud service is ensured.