Information processing method of low-density check codes

A technology of low-density check code and information processing method, applied in the field of information processing of low-density check code, can solve the problems of slow processing speed, complex processing, high cost, etc., to reduce power consumption, reduce hardware resources, and reduce costs Effect

Inactive Publication Date: 2010-09-01
SHANGHAI JIAO TONG UNIV
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Problems solved by technology

[0003] After searching the literature of the prior art, it was found that the Chinese patent application number is: 200710044708, and the name is: layered low-density check code decoder and decoding processing method, which provides a decoding of low-density check code Processing method, this technology utilizes the parallelism

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  • Information processing method of low-density check codes
  • Information processing method of low-density check codes
  • Information processing method of low-density check codes

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Embodiment

[0026] This embodiment includes the following steps:

[0027] In the first step, the sending end rotates and adjusts the check matrix H1 of the low-density check code to obtain the processed matrix H2.

[0028] The check matrix H1 of the low-density check code in this embodiment is a matrix of 4*16 rows and 8*16 columns, specifically as figure 1 As shown, where: the blank place means 0, and the dotted place means 1.

[0029] The described rotation adjustment process includes the following steps:

[0030] 1) Convert the parity check matrix H1 of the 4*16 rows and 8*16 columns low-density check code into a mother matrix M1 of 4 rows and 8 columns, each element in the mother matrix M1 represents a 16*16 matrix, Wherein: when the matrix of 16*16 is a zero matrix, the corresponding element in the mother matrix M1 is -1; otherwise, the element of the mother matrix M1 is the cyclic shift factor of the 16*16 cyclic shift identity matrix;

[0031] The mother matrix M1 obtained in th...

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Abstract

The invention relates to an information processing method of low-density check codes, which belongs to the field of communication technology. The method comprises the steps of: carrying out swivel adjustment on a check matrix H1 of the low-density check codes by a sending terminal to obtain a processed matrix H2; sending an initial data vector V by using a low-density check code encoder accordingto the matrix H2 to obtain a codeword vector X and sending the codeword vector X through channel; receiving a codeword vector Y by a receiving terminal and storing the codeword vector Y in a decoder buffer directly according to the order of reception; and receiving and processing the codeword vector Y by the receiving terminal by using the present layered low-density check code decoder to obtain a codeword vector Z, and then outputting the codeword vector Z directly according to the order of reception. The invention omits the input and output cyclic shift network for the low-density check code decoder, reduces the area and power consumption of the decoder, does not increase the processing complexity of the sending terminal and does not decrease the error correction of the codeword.

Description

technical field [0001] The invention relates to a method in the technical field of communication, in particular to an information processing method of a low-density check code. Background technique [0002] LDPC codes (low density parity check codes, low density check codes) are a coding technique first proposed by Gallager in 1963, which can be used as an error correction / error detection technique for various communication systems or information storage systems. Because of its performance approaching the channel limit, it has become a popular technology that has attracted the most attention in the past decade. LDPC code decoders usually have three structural forms: serial structure, full parallel structure, and partial parallel structure. The serial structure LDPC code decoder has a simple structure and consumes less hardware resources, but the decoding speed is slow and the throughput is low; the fully parallel structure has a fast decoding speed and high throughput, but ...

Claims

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Application Information

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IPC IPC(8): H03M13/11
Inventor 夏之晟俞晖徐友云崔靖王轶祥
Owner SHANGHAI JIAO TONG UNIV
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