Method for designing AES (Advanced Encryption Standard) encryption chip based on FPGA (Field Programmable Gate Array) and embedded encryption system

Abstract

The invention discloses a method for designing an AES (Advanced Encryption Standard) encryption chip based on an FPGA (Field Programmable Gate Array), which is designed for aiming at the requirement of an embedded system. The AES encryption chip not only can be used in a manner of a solid chip but also used in a manner of a software module. Three operation modes of ECB (Electronic Code Book), CBC (Cipher Block Chaining) and CTR (Counter Technical Requirement) are supported simultaneously. All standards of the AES can be encrypted and decrypted. The byte replacement and the key expansion are carried out by using a look-up table optimization algorithm. A column mixed optimization structure is provided. Device resources are saved while the operation speed is ensured. An RAM (Random-Access Memory) can be configured as a cache of information and a key through double ports of the FPGA. A problem for storing a time sequence and data of other devices or equipment and the FPGA is resolved. Safe and reliable communication with an FPGA interface joins CRC (Cyclic Redundancy Check) error detection in a manner of a memory bus. The AES encryption chip has the advantages of high safety, high encryption and decryption speeds, low device resource requirement, low cost and the like. The AES encryption chip can be widely used in information technology industries of intelligent card systems, ATMs (Automatic Teller Machines), wireless local area networks, wireless sensor networks and the like.

Description

technical field [0001] The invention relates to an IC chip and an embedded encryption system design method for encrypting and decrypting information and data. That is, it makes full use of the hardware reliability of FPGA and the flexibility of logic programming to realize the AES encryption algorithm, which also involves the design method of how to reduce device resources while ensuring the processing speed. This method supports all AES standards and three non- Feedback mode: electronic code book (ECB), cipher block chaining mode (CBC) and counter mode (CTR), and how this chip is applied to embedded systems. Background technique [0002] At present, the information technology industry at home and abroad needs encryption and decryption systems to improve information security, such as smart card systems (Smart Card), mobile banking systems (Cell Phone Bank), World Wide Web (WWW), ATM cash machines, wireless local area networks (WLAN), Wireless Sensor Network (WSN), etc. [...

AI Technical Summary

Problems solved by technology

[0007] After searching the literature of the prior art, it was found that the Chinese patent "Design method of AES encryption chip and computer encryption machine", publication number CN 10626289A, the patent on January 13, 2010, is an encryption designed for computer encryption machines. The chip reduces circuit resources by looking up the table method, but does not start from the theoretical algorithm of AES, further proposes a new method to reduce circuit resources, and does not consider the operation mode of AES and communication error detection

Images