Fixed-bit-width multiplier with high accuracy and low complexity properties

Abstract

The present invention relates to the technical field of integrated circuits, and in particular to a fixed-bit-width multiplier with high accuracy and low complexity properties. The fixed-bit-width multiplier of the present invention comprises a Booth encoding module, a partial product generation module, a partial product preprocessing module, a cutoff compensation module, a tree-shaped compression module and a binary adder module. An input port of the Booth encoding module is connected to external input data, and an output port of the Booth encoding module is connected to the partial product generation module and the partial product preprocessing module; the partial product generation module is connected to the external input data, and an output port of the partial product generation module is connected to the partial product generation module, the cutoff compensation module and the tree-shaped compression module; an output port of the partial product preprocessing module is connected to the cutoff compensation module and the tree-shaped compression module; and an output port of the cutoff compensation module is connected to the tree-shaped compression module, and an output port of the tree-shaped compression module is connected to an input port of the adder module. The fixed-bit-width multiplier of present invention has the beneficial effect of being suitable for use in operation scenes with high calculation accuracy requirements and low hardware complexity requirements.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a fixed-bit-width multiplier with high-precision and low-complexity characteristics. Background technique [0002] The multiplier is a very general digital unit module in the field of signal processing, widely used in fast Fourier transform, discrete cosine transform and digital filter. In digital signal processing applications, some blocks require the input and output to have the same bit width. For multiplication operations, fixed-bit-width multipliers are required. The difference between a fixed-bit-width multiplier and an ordinary multiplier lies in the number of digits of the result. In binary multiplication, an n-bit multiplicand is multiplied by an n-bit multiplier to obtain a 2n-bit product. The fixed-bit-width multiplier is due to its bit width Restricted, only the results of the upper n bits are retained, resulting in a certain error. The hardw...

AI Technical Summary

Problems solved by technology

[0003] At present, there are two kinds of fixed bit width multipliers that are more common. One is to directly cut off the low bits of each part and add the reserved high bits directly. This implementation method consumes the least hardware resources, but it will produce a large truncation error; The other is to keep all the partial product digits and accumulate them, and then round the result to keep the high part

The truncation error obtained by this implementation method is very small, but the hardware overhead is equivalent to a full-precision multiplier

Therefore, the current fixed bit width multiplier has the problem that the higher the precision, the higher the complexity

Images