Quasi-cyclic matrix high-speed multiplier in deep space communication based on lookup table

A quasi-circular matrix, deep space communication technology, applied in the field of channel coding, can solve the problems of wasting memory resources, large number of registers, high circuit power consumption, etc., and achieve the effect of reducing memory and logic resources, reducing power consumption, and simple structure

Inactive Publication Date: 2013-08-28
RONGCHENG DINGTONG ELECTRONICS INFORMATION SCI & TECH CO LTD
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Problems solved by technology

The disadvantage of this solution is that the number of registers is large, and a large number of AND gates are required to complete the multiplication operation and a large

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  • Quasi-cyclic matrix high-speed multiplier in deep space communication based on lookup table
  • Quasi-cyclic matrix high-speed multiplier in deep space communication based on lookup table
  • Quasi-cyclic matrix high-speed multiplier in deep space communication based on lookup table

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Embodiment Construction

[0032] The preferred embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, so that the advantages and features of the present invention can be more easily understood by those skilled in the art, so that the protection scope of the present invention can be defined more clearly.

[0033] Since the generator polynomial f of the circulant matrix i,j Rotating right by n bits is equivalent to rotating it left by b-n bits, that is Then formula (9) can be rewritten as

[0034] m i F i , j = e i X b f i , j l ( b ) + e i X b + 1 f i , j l ( b - 1 ) + · · · + e i X b + b - 1 f i , j l ( 1 )

[0035] = ( e i X b f i , j ) l ( b ) + ( e i X b + 1 f i , j ) l ( b - 1 ) + ·...

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Abstract

The invention provides a quasi-cyclic matrix high-speed multiplier in deep space communication based on a lookup table, and is used for realizing multiplication of a vector m and a quasi-cyclic matrix F in triangular encoding under multi-code quasi-cyclic low density parity check (QC-LDPC) approximation in the consultative committee for a space data system (CCSDS). The multiplier comprises four product lookup tables which are used for pre-storing possible algebraic sum of all generated polynomials in a binary field in block rows of all code matrixes F, four 2,048-bit binary summators for performing modulo-2 adding on outputs of the product lookup tables and contents of shift registers, and four 2,048-bit shift registers for storing the sum which is cyclically shifted 1 bit leftwards. The quasi-cyclic matrix high-speed multiplier is compatible with all the code types, so that the number of storage devices and logic resources are reduced; and the quasi-cyclic matrix high-speed multiplier has the advantages of simple structure, low power consumption, low cost and the like.

Description

Technical field [0001] The invention relates to the field of channel coding, in particular to a quasi-circulant matrix high-speed multiplier in the CCSDS deep-space communication standard multi-code QC-LDPC approximate lower triangular coding. Background technique [0002] Low-Density Parity-Check (LDPC) code is one of the efficient channel coding technologies, and QC-LDPC (Quasic-LDPC, QC-LDPC) code is a special LDPC code. The generator matrix G and the check matrix H of the QC-LDPC code are both arrays composed of cyclic matrices, which have the characteristics of segmented cyclic, so they are called QC-LDPC codes. The first row of the circulant matrix is ​​the result of the last row cyclically shifted to the right by 1 bit, and the remaining rows are the result of the previous row cyclically shifted to the right by 1 bit. Therefore, the circulant matrix is ​​completely characterized by its first row. Usually, the first row of the circulant matrix is ​​called its generator pol...

Claims

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Application Information

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IPC IPC(8): G06F7/523
Inventor 张鹏刘志文张燕
Owner RONGCHENG DINGTONG ELECTRONICS INFORMATION SCI & TECH CO LTD
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