17 results about "Critical path delay" patented technology

The invention provides an FPGA lookup table merging and decomposing method and device, equipment and a medium, and relates to the technical field of integrated circuit netlist optimization. The method comprises the following steps: acquiring a mapped LUT network of an FPGA; then, candidate pair identification is carried out on the LUT network, conflict-free LUT candidate pairs with the optimal weight are selected to be merged, an LUT connection relation graph is constructed after merging, and a key path is identified; on the basis of the LUT connection relation graph, decomposing the LUT on a non-critical path into smaller cascaded LUT units according to a LUT priority sequence; and dynamically updating the network topology structure and time sequence information of the LUT connection relation graph after each decomposition to complete optimization of the FPGA netlist. According to the method, the number of LUTs can be remarkably reduced and the resource utilization rate of the FPGA can be improved on the premise of ensuring that the delay of the critical path is not changed.

This invention relates to the field of integrated circuit technology and discloses a three-stage positive feedback comparator circuit and electronic device based on fast timing. The circuit includes a first-stage positive feedback module, a second-stage triggering and clocking module, a second-stage positive feedback amplification module, and a third-stage positive feedback latching module. By employing a three-stage positive feedback structure, this invention places the corresponding differential signal nodes in the same feedback loop at each stage, significantly enhancing the comparator's amplification rate and metastability suppression capability. Furthermore, by introducing a fast timing control mechanism, the second-stage amplification, clock reset generation, and third-stage latching operations can be executed in parallel, effectively shortening the critical path delay and significantly improving the overall comparison speed. The electronic device includes the aforementioned comparator circuit. This invention effectively solves the bottlenecks of traditional comparators in terms of speed and reliability and is suitable for high-speed, high-precision data conversion systems.

The invention provides a multi-agent reasoning optimization method and system based on Token calculation acceleration, and relates to the field of intelligent decision making, and the method comprises the steps: generating and maintaining a Token-level directed acyclic graph on line; constructing a reasoning path consistency sharing strategy, an approximate semantic sharing strategy and a forced sharing strategy to perform KV cache sharing; local change features are processed in an incremental coding mode, and context difference detection, incremental coding calculation and KV cache splicing are carried out; defining a contribution degree function for each Token so as to carry out Token contribution degree evaluation, and introducing a dynamic pruning mechanism based on the contribution degree; based on the Token-level directed acyclic graph, the parallel execution of the independent Token is realized through topology analysis and dynamic scheduling. According to the method, generation of redundant Token can be avoided, and the communication bandwidth and computing resources of the spacecraft are saved; the delay of the critical path is shortened, the decision-making efficiency of a multi-agent cooperation system can be improved, and the strict requirements of spacecraft tasks on the decision-making efficiency and the decision-making safety are met.

The application relates to the technical field of chip design, and particularly discloses a routing method and system based on timing criticality, which abstracts physical layout into a node network, constructs a weighted cost function of total wiring length and critical path length, adopts a minimum spanning tree algorithm to iteratively expand a path and record a parasitic parameter, calculates a merging cost value based on the product of the length of a coincident path and the timing criticality of a node, generates a virtual node by merging a node pair with the maximum benefit, and cyclically optimizes until a convergence condition is met, so that the dual objectives of wiring resource optimization and timing critical path delay reduction are achieved. The method is based on a more accurate time delay model, defines a target function which comprehensively considers the overall routing cost and the routing cost of a timing critical load node, makes timing analysis more accurate, reduces the signal delay and the size of a clock cycle of a load node according to the criticality of the load node, and effectively increases the running speed of a chip.

This invention discloses a binary adder array and method based on node decision, relating to the field of integrated circuits. It aims to solve the problems of high dynamic power consumption, reliance on critical path delay, and complex asynchronous adder circuitry in traditional adders. The method includes: calculating the carry propagation signal Pi and the carry generation signal Gi in parallel using operands A and B; generating a decision node Di for each bit i based on Pi and Gi; setting Di low when Gi=1, setting Di high when Gi=0 and Pi=0, and assigning the state Di-1 to Di when Pi=1; generating the next bit sum signal Si+1 based on Di; outputting ~Pi+1 when Di is low, and outputting Pi+1 when Di is high. Signal transmission is achieved by controlling the on / off state of physical channels, rather than cascading logic gates. The device includes a logic operation module and an output control module. The output control module includes a node control network with level injection units and level transmission switches, all connected to the decision node Di. This invention also provides an asynchronous adder array composed of multiple cascaded adder units and a chip integrating this circuit. This invention achieves conditional signal propagation through a unique decision node network and physical channel control, which can significantly reduce dynamic power consumption when the input data is sparse, and naturally supports asynchronous operation, with the advantages of high energy efficiency and easy expansion.

The application discloses a kind of digital filter structures for Σ-ΔADC downsampling, adopt full digital method to construct three-order single loop feedforward system, series integrated integral-comb cascaded filter, compensation filter and half-band filter.Integral-comb cascaded filter is composed of multistage integrator series recursion structure, support downsampling multiple programmable, improve parallelism and hardware utilization by moving delay unit position in advance.Compensation filter adopts odd-order integrator multi-branch parallel, reduce resource occupation, significantly improve processing speed;Half-band filter uses retiming technology to adjust coefficient position, reduce critical path delay, improve the highest frequency of system, while reducing the amount of calculation through symmetric structure and multiplexing extraction path, front extraction reduces the demand of operation rate and data loss.The application realizes low power consumption, low hardware consumption and high design flexibility of downsampling filter in Σ-ΔADC digital module.

The invention discloses a cryptographic algorithm hardware implementation method based on Montgomery modular multiplication. A hardware circuit comprises an APB interface module, a host register interface module, a control logic module, an IRQ interface module and an RSA core operation module. According to the hardware implementation method, loading of RSA parameters and result output are achieved through a host register interface. And full-process control from data loading, Montgomery domain conversion, modular exponentiation iterative operation to final result output is realized through a control logic module and an internal state machine. A high-base Montgomery algorithm is adopted in the RSA core operation module to be combined with a base 4 Booth carry-save multiplier and a CSA partial product compressor, parallel operation of a multi-stage depth assembly line is achieved, and a modular multiplier of 12-path parallel operation is adopted outside the RSA core operation module to achieve an external assembly line structure. Through cooperative processing of internal and external double-layer assembly lines, the delay of a critical path is remarkably shortened, and the throughput rate of modular exponentiation calculation and the utilization rate of hardware resources are improved.

The application provides a low-delay pseudo-random function implementation method supporting error detection, comprising the following steps: step 1, obtaining and copying a 128-bit input message; step 2, generating a round key; step 3, performing a pseudo-random function operation to obtain a 128-bit initial output; and step 4, performing an error detection mechanism to obtain a 128-bit final output. Through the whole-process cooperative design from a nonlinear S-box to a complete pseudo-random function construction, the application realizes the minimization of the critical path delay, significantly reduces the hardware delay compared with the existing low-delay cryptography primitives, and is more suitable for the low-delay requirements of the Internet of Things platform. The application sets an error detection mechanism based on a linear block code at the algorithm level, detects the transmission errors and countermeasure fault injection induced by environmental interference with a small area cost, and fills the gap of the existing low-delay cryptography primitives in the reliability design.

The application provides a FPGA lookup table merging and decomposition method, device, equipment and medium, and relates to the integrated circuit netlist optimization technical field.The application obtains a mapped LUT network of the FPGA;then, candidate pair identification is performed on the LUT network, a conflict-free and optimal-weight LUT candidate pair is selected for merging, and a LUT connection relationship graph is constructed after the merging, and a critical path is identified;based on the LUT connection relationship graph, LUTs on a non-critical path are decomposed into smaller cascade LUT units in the order of LUT priority;after each decomposition, the network topology structure and timing information of the LUT connection relationship graph are dynamically updated, and the optimization of the FPGA netlist is completed.The application can significantly reduce the number of LUTs and improve the FPGA resource utilization rate under the premise of ensuring that the delay of the critical path remains unchanged.

The invention relates to the technical field of integrated circuits, and discloses a three-stage positive feedback comparator circuit based on a fast time sequence and electronic equipment. The circuit comprises a first-stage positive feedback module, a second-stage trigger and clock module, a second-stage positive feedback amplification module and a third-stage positive feedback latch module. According to the invention, a three-stage positive feedback structure is adopted, and corresponding differential signal nodes are arranged in the same feedback loop at each stage, so that the amplification rate and the metastable state suppression capability of the comparator are obviously enhanced; and by introducing a rapid time sequence control mechanism, second-stage amplification, clock reset generation and third-stage latch operation can be executed in parallel, so that the key path delay is effectively shortened, and the overall comparison speed is greatly improved. The electronic equipment comprises the comparator circuit. The invention effectively solves the bottleneck of the traditional comparator in the aspects of speed and reliability, and is suitable for a high-speed and high-precision data conversion system.

The application belongs to the field of integrated circuits, and particularly relates to a FPGA layout method based on reinforcement learning. First, according to an input netlist file, logical units contained in a FPGA design circuit are extracted, and then initialization layout operation of the logical units is completed; in view of the slow convergence problem of a traditional simulated annealing method layout, multiple search region construction methods are proposed, which can effectively improve the search efficiency of the layout solution space; on this basis, an optimal search region selection method based on reinforcement learning is proposed, which can adaptively select the optimal search region to perform the exchange operation of the logical units. The layout method can greatly reduce the time required for FPGA layout while maintaining the required wire length and critical path delay.

The application discloses a constant decomposition and cooperative optimization-based hardware construction method and system for a modulus multiplier. The method comprises the following steps: obtaining an original constant modulus multiplication operation, decomposing a large-bit-width constant to obtain an expression composed of small-bit-width parameters through multiplication and addition and subtraction operations, wherein each level of decomposition splits a current level value into a combination of a high-bit part and a low-bit part, and each parameter value is limited in a modulus range; based on a regular signed number coding method, converting each small-bit-width parameter obtained through decomposition into a binary representation form with the least non-zero bits to determine the least number of adders required for multiplication of each parameter; in combination with the characteristics of a modulus reduction algorithm, evaluating the resource consumption and critical path delay of different decomposition expressions during hardware construction; and through iterative optimization, selecting a decomposition expression with the least number of adders under the constraint of critical path delay to generate a hardware circuit structure of a constant modulus multiplier. The application can effectively reduce resource consumption and improve operation speed.

The application provides a configurable modulo multiplier, comprising an n*n-bit binary multiplier, a bit extractor, an (n-1-k)*k-bit binary multiplier, a first configuration register stack, a compression tree adder, a second configuration register stack, an n+1-bit adder, a 2-bit adder, a carry-save adder, an n+2-bit adder and a modulo correction unit. The configurable modulo multiplier of the application proposes a new modulo correction scheme for high-bit partial product modulo correction, greatly reduces the configuration capacity of the configurable general-purpose modulo multiplier, reduces the critical path delay of the general-purpose modulo multiplier, and solves the variable remainder base requirement of the remainder system application compared with the prior art. By completely separating the multiplier and the modulo correction part, the hardware compatibility problem of the regular application and the remainder application is solved.

This application relates to the field of digital communication technology and discloses a method, apparatus, decoder, and storage medium for calculating the Galois field index. The method includes: performing a group indexing operation on the target index to obtain a base address and an offset within the group; reading the corresponding base value from a pre-stored compressed index table based on the base address; wherein the index entries stored in the compressed index table are subsets selected at equal intervals with a fixed step size from the original complete index space, and the fixed step size is an integer power of 2 greater than 1; and performing a single-step recursive operation corresponding to the number of times the offset within the group is set based on the base value and the offset within the group to generate the Galois field element value corresponding to the target index. This application can reduce the storage and wiring overhead of Galois field index calculation and shorten the critical path delay.

This invention discloses a highly parallel rejection sampler for post-quantum cryptography and its operating method. The 8-bit sampled data is split into symmetrical high-4 and low-4 bit parallel sampling units: the high-4 bit unit performs data compression towards the least significant bit, and the low-4 bit unit performs data compression towards the most significant bit. The two compressed outputs are combined through physical splicing to form a pre-aligned data stream with continuous data in the middle and possible invalid data bits at the beginning and end. Subsequently, the system uses the effective data count value of the high-bit unit as a control signal to drive a multiplexer network to directly select the output result according to five preset alignment paths, thereby achieving a compact arrangement of fully parallel data. This invention avoids the complex multi-level shift operations in traditional architectures, greatly optimizes critical path latency and hardware resource overhead, and is suitable for high-speed hardware accelerator design for post-quantum cryptography algorithms.

The invention discloses a local-cloud collaborative RTL code optimization method for IP security. The method comprises the following steps: step 1, constructing K pairs of proprietary modules and first draft by using a local large language model; step 2, extracting an optimization principle set from a proprietary module to a first draft according to a local principle; 3, performing IP leakage risk detection verification on the optimization principle set by using a local large language model; step 4, feeding back the leakage feedback value to the local large language model, and repeating the step 2 to the step 4 until the leakage verification of the optimization principle set is passed; and 5, uploading the optimization principle set passing the leakage verification to the cloud big language model, and optimizing the target module to be optimized. According to the method, the optimization success rate of 50.85% is achieved in a key path delay optimization task; and the optimization success rate reaches 66.67% in a power consumption optimization task. According to the method, on the premise of ensuring the safety of intellectual property, the hardware description language code can be effectively optimized by utilizing the optimization capability of the cloud large model.

The application relates to the technical field of computer architecture, and discloses a memory-computing integrated large language model DRAM fault-tolerant method, which comprises the following steps: constructing a space-time related multi-granularity DRAM fault model, defining a memory bank level space constraint, and a single-bit or multi-bit flip fault mode, and establishing a DRAM fault probability calculation method based on the Arrhenius formula; performing multi-precision and module level fault sensitivity quantitative analysis on the large language model; based on the fault sensitivity quantitative result, performing precision-aware bit-level differentiated fault injection, and using a fine-tuning framework of a low-rank self-adaptive adapter based on module heterogeneity perception to perform fault-tolerant enhancement on the target large language model; the application has small parameter redundancy, does not add a hardware error correction circuit, and does not increase the hardware critical path delay, thereby improving the tolerance and robustness of the large language model to single-bit and multi-bit flip faults under the DRAM memory-computing integrated architecture.