7 results about "Critical path delay" patented technology

The application relates to the technical field of chip design, and particularly discloses a routing method and system based on timing criticality, which abstracts physical layout into a node network, constructs a weighted cost function of total wiring length and critical path length, adopts a minimum spanning tree algorithm to iteratively expand a path and record a parasitic parameter, calculates a merging cost value based on the product of the length of a coincident path and the timing criticality of a node, generates a virtual node by merging a node pair with the maximum benefit, and cyclically optimizes until a convergence condition is met, so that the dual objectives of wiring resource optimization and timing critical path delay reduction are achieved. The method is based on a more accurate time delay model, defines a target function which comprehensively considers the overall routing cost and the routing cost of a timing critical load node, makes timing analysis more accurate, reduces the signal delay and the size of a clock cycle of a load node according to the criticality of the load node, and effectively increases the running speed of a chip.

This invention discloses a binary adder array and method based on node decision, relating to the field of integrated circuits. It aims to solve the problems of high dynamic power consumption, reliance on critical path delay, and complex asynchronous adder circuitry in traditional adders. The method includes: calculating the carry propagation signal Pi and the carry generation signal Gi in parallel using operands A and B; generating a decision node Di for each bit i based on Pi and Gi; setting Di low when Gi=1, setting Di high when Gi=0 and Pi=0, and assigning the state Di-1 to Di when Pi=1; generating the next bit sum signal Si+1 based on Di; outputting ~Pi+1 when Di is low, and outputting Pi+1 when Di is high. Signal transmission is achieved by controlling the on / off state of physical channels, rather than cascading logic gates. The device includes a logic operation module and an output control module. The output control module includes a node control network with level injection units and level transmission switches, all connected to the decision node Di. This invention also provides an asynchronous adder array composed of multiple cascaded adder units and a chip integrating this circuit. This invention achieves conditional signal propagation through a unique decision node network and physical channel control, which can significantly reduce dynamic power consumption when the input data is sparse, and naturally supports asynchronous operation, with the advantages of high energy efficiency and easy expansion.

The application provides a low-delay pseudo-random function implementation method supporting error detection, comprising the following steps: step 1, obtaining and copying a 128-bit input message; step 2, generating a round key; step 3, performing a pseudo-random function operation to obtain a 128-bit initial output; and step 4, performing an error detection mechanism to obtain a 128-bit final output. Through the whole-process cooperative design from a nonlinear S-box to a complete pseudo-random function construction, the application realizes the minimization of the critical path delay, significantly reduces the hardware delay compared with the existing low-delay cryptography primitives, and is more suitable for the low-delay requirements of the Internet of Things platform. The application sets an error detection mechanism based on a linear block code at the algorithm level, detects the transmission errors and countermeasure fault injection induced by environmental interference with a small area cost, and fills the gap of the existing low-delay cryptography primitives in the reliability design.

The application discloses a constant decomposition and cooperative optimization-based hardware construction method and system for a modulus multiplier. The method comprises the following steps: obtaining an original constant modulus multiplication operation, decomposing a large-bit-width constant to obtain an expression composed of small-bit-width parameters through multiplication and addition and subtraction operations, wherein each level of decomposition splits a current level value into a combination of a high-bit part and a low-bit part, and each parameter value is limited in a modulus range; based on a regular signed number coding method, converting each small-bit-width parameter obtained through decomposition into a binary representation form with the least non-zero bits to determine the least number of adders required for multiplication of each parameter; in combination with the characteristics of a modulus reduction algorithm, evaluating the resource consumption and critical path delay of different decomposition expressions during hardware construction; and through iterative optimization, selecting a decomposition expression with the least number of adders under the constraint of critical path delay to generate a hardware circuit structure of a constant modulus multiplier. The application can effectively reduce resource consumption and improve operation speed.

This application relates to the field of digital communication technology and discloses a method, apparatus, decoder, and storage medium for calculating the Galois field index. The method includes: performing a group indexing operation on the target index to obtain a base address and an offset within the group; reading the corresponding base value from a pre-stored compressed index table based on the base address; wherein the index entries stored in the compressed index table are subsets selected at equal intervals with a fixed step size from the original complete index space, and the fixed step size is an integer power of 2 greater than 1; and performing a single-step recursive operation corresponding to the number of times the offset within the group is set based on the base value and the offset within the group to generate the Galois field element value corresponding to the target index. This application can reduce the storage and wiring overhead of Galois field index calculation and shorten the critical path delay.

This invention discloses a highly parallel rejection sampler for post-quantum cryptography and its operating method. The 8-bit sampled data is split into symmetrical high-4 and low-4 bit parallel sampling units: the high-4 bit unit performs data compression towards the least significant bit, and the low-4 bit unit performs data compression towards the most significant bit. The two compressed outputs are combined through physical splicing to form a pre-aligned data stream with continuous data in the middle and possible invalid data bits at the beginning and end. Subsequently, the system uses the effective data count value of the high-bit unit as a control signal to drive a multiplexer network to directly select the output result according to five preset alignment paths, thereby achieving a compact arrangement of fully parallel data. This invention avoids the complex multi-level shift operations in traditional architectures, greatly optimizes critical path latency and hardware resource overhead, and is suitable for high-speed hardware accelerator design for post-quantum cryptography algorithms.

The application relates to the technical field of computer architecture, and discloses a memory-computing integrated large language model DRAM fault-tolerant method, which comprises the following steps: constructing a space-time related multi-granularity DRAM fault model, defining a memory bank level space constraint, and a single-bit or multi-bit flip fault mode, and establishing a DRAM fault probability calculation method based on the Arrhenius formula; performing multi-precision and module level fault sensitivity quantitative analysis on the large language model; based on the fault sensitivity quantitative result, performing precision-aware bit-level differentiated fault injection, and using a fine-tuning framework of a low-rank self-adaptive adapter based on module heterogeneity perception to perform fault-tolerant enhancement on the target large language model; the application has small parameter redundancy, does not add a hardware error correction circuit, and does not increase the hardware critical path delay, thereby improving the tolerance and robustness of the large language model to single-bit and multi-bit flip faults under the DRAM memory-computing integrated architecture.