Method for hierarchically identifying circuit gate based on workload

A work load and circuit identification technology, applied in the direction of constraint-based CAD, CAD circuit design, electrical digital data processing, etc., can solve the problem of circuit inapplicability, not considering the aging state of the circuit, etc., to improve work efficiency and avoid duplication. The effect of processing and good guiding significance

Pending Publication Date: 2020-09-11
JIANGNAN UNIV
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Problems solved by technology

However, this method is to simulate the logic gate, establish the aging delay degradation characteristics, and then analyze it with the target netlist. Although

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  • Method for hierarchically identifying circuit gate based on workload
  • Method for hierarchically identifying circuit gate based on workload
  • Method for hierarchically identifying circuit gate based on workload

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Experimental program
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Embodiment 1

[0047] This embodiment provides a method for hierarchically identifying circuit gates based on workload, the method including:

[0048] S1 performs static timing analysis according to the circuit netlist and constraint files, and obtains the original delay value set of the timing path inside the circuit, which is defined as the original delay set D p ={d p1 , d p2 ,...,d pj ,...,d pn}, where n represents the number of original paths. And sort the original delay sequence of the circuit to find out the maximum delay T of the circuit without considering the aging delay max ; The original delay value is the sum of the delays of each aging gate circuit;

[0049] S2 traverses the original delayed collection D p , if d pj ×(1+R%)>T max , then define d pj The corresponding path is a potential path considering the aging condition, which is written into the potential critical path set RCP until the original delay set D p End the traversal when it is empty; among them, R% takes...

Embodiment 2

[0061] This embodiment provides a practical application of a method for hierarchically identifying circuit gates based on workload. The method includes:

[0062] Step 1: Obtain the workload signal and extract the probability of the workload signal;

[0063] For the design of microprocessors, use a performance simulator to extract the workload; for example, use a performance simulator to extract the input patterns of the different functional blocks of the processor of the target application.

[0064] For other designs, such as ASICs, high-level (system-level) simulation vectors can be used for performance analysis. That is, profiling data containing system-level workload-related data is provided to step 2 for further processing for timing analysis.

[0065] With this approach, a link is established between system-level workload dependencies (that is, occur at runtime) and timing analysis at design time.

[0066] Step 2: The information obtained from the system-level workload ...

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Abstract

The invention discloses a method for hierarchically identifying a circuit gate based on a workload, and belongs to the field of high reliability of high-performance processors. The method comprises: obtaining a workload signal, and, in a signal probability extracting stage, reading a circuit net list and design constraints, obtaining path delay of a circuit, and obtaining a potential critical path. The method comprises the signal probability extracting stage, a parameter analysis and calculation stage and a hierarchical identification gate determination stage. The parameter analysis and calculation stage is used for calculating the maximum critical path delay which can be borne by the circuit path and is obtained by aging delay degradation under the effect of the NBTI; and the hierarchicalidentification gate determination stage, which is used for determining a gate with relatively high aging sensitivity in the critical path, and proposing a new weight calculation method, and sorting the determined circuit gates according to the weights so as to perform hierarchical batch processing on the gate circuit. The method can be integrated in the ASIC design process, the aging critical path and the aging critical door can be effectively identified, the complexity of replacing the door in the critical path in a traditional method is reduced, and the working efficiency is improved.

Description

technical field [0001] The invention relates to a method for hierarchically identifying circuit gates based on workload, and belongs to the high-reliability field of high-performance processors. Background technique [0002] With the development of very large-scale integrated circuits and the continuous improvement of manufacturing technology, integrated circuits have entered the nanometer era. In ultra-deep CMOS processability, reliability issues have become the main factors to be considered. Designing reliable circuits that can operate for long periods of time, especially while ensuring correct function under varying operating environments, has become a very difficult challenge. [0003] For reliability, negative bias temperature instability (Negative Bias Temperature Instability, NBTI) refers to the degradation of a series of electrical parameters caused by applying negative gate voltage to PMOSFET at high temperature. In ultra-deep CMOS processability, reliability Ques...

Claims

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Application Information

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IPC IPC(8): G06F30/33G06F30/337G06F119/02G06F119/04G06F111/04
CPCG06F30/33G06F30/337G06F2119/02G06F2119/04G06F2111/04
Inventor 虞致国刘帅顾晓峰魏敬和
Owner JIANGNAN UNIV
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