Method for hierarchically identifying circuit gate based on workload

Abstract

The invention discloses a method for hierarchically identifying a circuit gate based on a workload, and belongs to the field of high reliability of high-performance processors. The method comprises: obtaining a workload signal, and, in a signal probability extracting stage, reading a circuit net list and design constraints, obtaining path delay of a circuit, and obtaining a potential critical path. The method comprises the signal probability extracting stage, a parameter analysis and calculation stage and a hierarchical identification gate determination stage. The parameter analysis and calculation stage is used for calculating the maximum critical path delay which can be borne by the circuit path and is obtained by aging delay degradation under the effect of the NBTI; and the hierarchicalidentification gate determination stage, which is used for determining a gate with relatively high aging sensitivity in the critical path, and proposing a new weight calculation method, and sorting the determined circuit gates according to the weights so as to perform hierarchical batch processing on the gate circuit. The method can be integrated in the ASIC design process, the aging critical path and the aging critical door can be effectively identified, the complexity of replacing the door in the critical path in a traditional method is reduced, and the working efficiency is improved.

Description

technical field [0001] The invention relates to a method for hierarchically identifying circuit gates based on workload, and belongs to the high-reliability field of high-performance processors. Background technique [0002] With the development of very large-scale integrated circuits and the continuous improvement of manufacturing technology, integrated circuits have entered the nanometer era. In ultra-deep CMOS processability, reliability issues have become the main factors to be considered. Designing reliable circuits that can operate for long periods of time, especially while ensuring correct function under varying operating environments, has become a very difficult challenge. [0003] For reliability, negative bias temperature instability (Negative Bias Temperature Instability, NBTI) refers to the degradation of a series of electrical parameters caused by applying negative gate voltage to PMOSFET at high temperature. In ultra-deep CMOS processability, reliability Ques...

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Problems solved by technology

However, this method is to simulate the logic gate, establish the aging delay degradation characteristics, and then analyze it with the target netlist. Although it is relatively simple and fast, it does not take into account the aging state of the circuit in the actual operating state. For complex circuits not applicable

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