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Semiconductor device

A semiconductor and device technology, applied in the field of semiconductor devices, can solve the problems of low storage capacity of pattern memory, small total number of test steps, short test time, etc., and achieve high efficiency

Inactive Publication Date: 2007-12-12
PANASONIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, when considering the efficiency of the screening check, a smaller total number of test steps is desired, preferably a shorter total test time, in addition to a lower storage capacity of the pattern memory

Method used

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  • Semiconductor device
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  • Semiconductor device

Examples

Experimental program
Comparison scheme
Effect test

no. 1 example approach

[0024] FIG. 1 is a block diagram for showing the structure of a semiconductor device 100 according to a first embodiment mode of the present invention. As shown in FIG. 1, the semiconductor device 100 of the first embodiment mode is an LSI (Large Scale Integration), which is equipped with a memory 101, a normal operation path 103, a memory BIST (built-in self-test) circuit 105, a test operation path 107 , a delay circuit 109 , and a selector 111 . The LSI has a function for self-testing the memory 101 .

[0025] The normal operation path 103 is within the semiconductor device 100 and corresponds to a critical path defined from a flip-flop (FF) 113 of a data processing unit (not shown) to the memory 101 . The memory BIST circuit 105 performs timing analysis (STA) of the normal operation path 103, generates a test pattern, and performs a failure test for the memory 101 by using the generated test pattern. This test operation path 107 corresponds to the path defined from the me...

no. 2 example approach

[0031] FIG. 4 is a block diagram for showing the structure of a semiconductor device 200 according to a second embodiment mode of the present invention. The semiconductor device 200 of this second embodiment mode differs from the semiconductor device 100 as described in the first embodiment mode in the following points. That is, in the second embodiment mode, the memory 151 is provided outside the semiconductor device 200, and the delay value set to the delay circuit 201 is variable. Except for the above points, other points are similar to those in the first embodiment mode, and the same reference numerals shown in FIG. 1 have been used as those for explaining commonly used structural elements shown in FIG. 4 . Since the delay amount of the delay circuit 201 is variable, the performance of the normal operation path 103 can be evaluated.

[0032] It should also be noted that the delay circuit 201 of the second embodiment mode may alternatively include a fuse (not shown) in wh...

no. 3 example approach

[0034] FIG. 5 is a block diagram for showing the structure of a semiconductor device 300 according to a third embodiment mode of the present invention. The semiconductor device 300 of this third embodiment differs from the semiconductor device 100 described in the first embodiment in the following points. That is, in the third embodiment mode, the memory 151 is provided outside the semiconductor device 300 , and the output terminal 301 of the semiconductor device 300 is provided at the output terminal of the selector 111 . The output terminal 301 is connected to the externally provided memory 151 . Except for the above points, other points are similar to those in the first embodiment mode, and the same reference numerals shown in FIG. 1 have been used as those for explaining commonly used structural elements shown in FIG. 5 . The output terminal 301 has a circuit (not shown) that switches the current level of each signal output from the selector 111 . Alternatively, the ext...

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PUM

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Abstract

A semiconductor device equipped with: a logic circuit, such as a memory; a self-test circuit, for self-testing the logic circuit; a critical path, defined as up to the logic circuit; a test path, defined as from the self-test circuit until the logic circuit; a delay circuit, Provided on the test path for setting the same delay value as that of the critical path; and a selection / output circuit for selecting any one of a signal input via the critical path and another signal input via the test path , and output the selected signal.

Description

technical field [0001] The present invention relates to a semiconductor device capable of performing screening inspection with higher efficiency. Background technique [0002] As semiconductor devices have been highly integrated and operated at high speeds, reductions in width with respect to transistors and wirings have rapidly progressed. However, if a very fine technique of the manufacturing process is advanced, failures can easily occur due to fluctuations in the process, and slight defects occurring during the manufacturing operation. As a result, BIST (Built-In Self-Test) has been used as a test method capable of assuring actual operation. [0003] For example, an LSI equipped with memory and paths and having a self-test function has a memory BIST circuit incorporated thereon. As shown in FIG. 6, when the LSI performs a screening check due to the self-test function, the memory BIST circuit performs timing analysis (STA: Static Timing Analysis) for a critical path def...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/26H01L21/66
CPCG11C29/48G11C29/1201G01R31/3016G11C29/50012G01R31/3187G11C29/50
Inventor 山口德志
Owner PANASONIC CORP
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