Rounding prediction method for floating point adder

Abstract

The invention discloses a rounding prediction method for a floating point adder. The performance of the adder can be improved. A rounding prediction unit realized by using the method works in parallel with a mantissa adder of the adder to generate a normalized displacement control signal and a mantissa adjustment control signal including rounding information. A mantissa and an index are adjusted by a post-order unit by using the normalized displacement control signal, so that a normalized result including round-up information can be obtained; the displaced mantissa is then adjusted by using the mantissa adjustment control signal, so that a final result of the adder can be obtained. Thus, according to the adder using the prediction unit, symbol confirmation and rounding operations are successfully fallen into the normalization operation, and the operation of two-stage consumption time in the adder is reduced. The area and the critical path delay of the unit are not increased with the increase in precision of the operation processed by the unit, so that the method is particularly suitable for a high-precision adder and is realized through a super-large-scale integrated circuit.

Description

【Technical field】 [0001] The invention relates to a rounding prediction method, in particular to a rounding prediction method for a floating-point adder. 【Background technique】 [0002] Literature "G.Dimitrakopoulos, K.Galanopoulos, C.Mavrokefalidis, D.Nikolos, Low-power leading-zero counting and anticipation logic for high-speed floating point units, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, July2008 , Volume16, Issue7, pp.837-850." The leading 0, 1 prediction unit involved is a computing unit widely used to improve the performance of floating-point adders today. Using the floating-point adder of this unit, it is not necessary to wait for the calculation result of the mantissa addition while calculating the mantissa addition, and directly predict the number of leading 0 and 1 by processing the mantissa values ​​of the two operands, so that the leading The 0, 1 check latency is removed from the critical path latency of the floating point adder. Tha...

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Problems solved by technology

[0004] It is not difficult to see that in the above two popular methods of improving the floating-point adder algorithm, additional computing units are used to shorten the critical path delay of the floating-point adder through parallel computing, but the calculation process is very complicated. Moreover, with the improvement of calculation accuracy, the unit area, power consumption, and delay all increase significantly.

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