Efficient circuits for out-of-order microprocessors

Abstract

The poor scalability of existing superscalar processors has been of great concern to the computer engineering community. In particular, the critical-path delays of many components in existing implementations grow quadratically with the issue width and the window size. This patent presents a novel way to reimplement these components and reduce their critical-path delay growth. It then describes an entire processor microarchitecture, called the Ultrascalar processor, that has better critical-path delay growth than existing superscalars. Most of our scalable designs are based on a single circuit, a cyclic segmented parallel prefix (cspp). We observe that processor components typically operate on a wrap-around sequence of instructions, computing some associative property of that sequence. For example, to assign an ALU to the oldest requesting instruction, each instruction in the instruction sequence must be told whether any preceding instructions are requesting an ALU. Similarly, to read an argument register, an instruction must somehow communicate with the most recent preceding instruction that wrote that register. A cspp circuit can implement such functions by computing for each instruction within a wrap-around instruction sequence the accumulative result of applying some associative operator to all the preceding instructions. A cspp circuit has a critical path gate delay logarithmic in the length of the instruction sequence. Depending on its associative operation and its layout, a cspp circuit can have a critical path wire delay sublinear in the length of the instruction sequence.

Description

CROSS REFERENCE TO RELATED APPLICATIONS [0001] This application claims the benefit of Provisional Application Ser. No. 60 / 077,669, filed Mar. 12, 1998, and Provisional Application Ser. No. 60 / 108,318, filed Nov. 13, 1998, both of which are incorporated herein by reference in their entireties.1. BACKGROUND OF THE INVENTION [0002] This invention draws from two different areas: parallel-prefix circuits and superscalar-processor circuits. Parallel-prefix circuits have, in the past, been most often used for parallel computation in machine such as the Connection Machine CM-5 supercomputer. (See, for example, [25, 18, 16, 7, 2].) Throughout this patent, numbers enclosed in square brackets refer to the references cited in Section 4.4 below, each of which is incorporated by reference herein. [0003] Superscalar processor circuits are used to implement processors that exploit instruction-level parallelism (ILP) using out-of order execution. Instruction-level parallelism is the parallelism that...

AI Technical Summary

Benefits of technology

The patent describes a new improvement to a circuit called the parallel prefix circuit, which can be used in a superscalar processor. This improvement involves allowing the prefix operation to "wrap around" from the end back to the beginning, which is called Cyclic Segmented Parallel Prefix (CSPP). CSPP circuits can improve the performance of many circuits in a superscalar processor and are especially useful when the window fills up or wraps around. The invention also includes a number of other novel circuits that can improve performance, but are not prefix circuits. The circuits used in the invention grow much more slowly than those of a superscalar processor and have similar memory bandwidth to today's processors. The Ultrascalar processor, which breaks the scalability barrier by restructuring the microarchitecture of the processor, eliminates the need for separate renaming logic, wake-up logic, bypass logic, and multi-ported register files.

Problems solved by technology

This problem is referred to as a “write-after-read” hazard.

When scaled up, the circuitry used in the 21264 for compressing the window requires large area and has long critical-path lengths, however.

When the reorder buffer fills up, some processors exhibit performance anomalies.

Some processors wrap around, but start scheduling newer instructions instead of older ones, which can hurt performance.

Propagation delay consists of delays through both gates and wires, or alternately of delays through transistors driving RC networks.

Increasing the number of pipeline stages offers diminishing returns, however, as pipeline registers begin to take up a greater fraction of every clock cycle and as more clock cycles are needed to resolve data and control hazards.

The critical-path delays of many of today's processor circuits do not scale well.

Increasing issue widths and increasing window sizes are threatening to explode the cycle time of the processor.

Images