141 results about "Approximate computing" patented technology

Workloads for executing a graph neural network (GNN) may be divided among various processing units, such as a central processing unit (CPU) and a neural processing unit (NPU). The NPU may include a data processing unit (DPU) and a digital signal processor (DSP). The CPU may perform precomputation, model optimization, hardware optimization, and compilation. For example, the CPU may precompute a parameter matrix and use the parameter matrix as internal parameters of a GNN. The CPU may also perform node padding, approximation computation, or transfer of DSP operations to DPU to optimize the GNN. The CPU may also perform sparsity data compute and storage, vertical fusion of DSP operations and DPU operations, or data quantization to optimize performance of the NPU. The compiled GNN may be provided to the NPU, and the DPU and DSP may perform the operations in the compiled GNN to produce a prediction of the GNN.

To provide a feasible solution search device and a feasible solution search method with which it is possible to search for a feasible solution capable of establishing multi-performance, in designing a rear suspension system of a vehicle.SOLUTION: A feasible solution search method includes the steps of: setting design specifications and performance values through confirmation of performance and specifications to be satisfied; filling a design space according to design of experiments; generating a regression model in a prediction model of response values by using machine learning; performing optimization on the basis of constraint conditions; determining design specification values of a rear suspension system; generating displacement vector candidates from initial individual generation in the optimization; performing approximate calculation allowing continuous evaluation of the maximum value of the amount of deviation from a plurality of response constraint ranges by using the KS function, selecting an individual at a distance farthest from an existing solution in a feasible region; and dividing a population into a plurality of partial populations to execute the optimization.SELECTED DRAWING: Figure 3

This invention discloses a low-complexity decoding method for LDPC-Hadamard codes based on a prototype diagram, belonging to the field of digital signal processing. The implementation method is as follows: information bits are LDPC encoded, and then the constraint relationship of the check nodes of the LDPC code is encoded into Hadamard code to obtain the prototype diagram of the LDPC-Hadamard code; the encoded codewords are transmitted and received through a channel, and the PVN and HCN nodes are initialized with the received information; Hadamard decoding is performed using a symbol-by-symbol maximum a posteriori probability decoding algorithm, and DFHT approximation is used to reduce decoding complexity; the decoded information is transmitted to the PVN nodes; the updated HCN node information is summed with the information from the previous iteration, and the summation result is used to determine the decoding; a decoding decision is made on the PVN information, and decoding is performed. This invention combines LDPC encoding, Hadamard encoding, and Max-Log approximation calculation methods to reduce decoding complexity and enhance the stability and reliability of the communication system.

The invention provides a dynamic intelligent target detection system and method based on a reasoning, namely a training normal form, and the system comprises a real-time learning module which carries out the real-time reasoning of input data through a YOLOX model, monitors a model reasoning result in real time, and triggers and activates the online learning according to the needs; the parameter fusion engine is used for training a model needing online learning, calculating parameter sensitivity based on Hessian matrix approximation by applying a gradient importance sorting algorithm, filtering abnormal node gradients through a difference perception aggregation protocol and by using cosine similarity, and realizing stable parameter transition through momentum updating by adopting progressive knowledge fusion; the multi-stage verification subsystem is used for carrying out automatic inspection on the trained model; and the resource awareness controller is used for dynamically adjusting resource allocation and gradient sparse transmission by acquiring hardware resource conditions in real time. The real-time performance, the accuracy and the environment adaptability of target detection can be remarkably improved, and it is ensured that the model efficiently runs on different hardware platforms.

The invention relates to a big data real-time monitoring system and method. The big data real-time monitoring system comprises a data access module, a preprocessing standardization module, a streaming computation module, a rule model engine module, an alarm arrangement and disposal module, a storage query module and a visualization and operation and maintenance module. The data access module is used for collecting multi-source heterogeneous data from a message queue, a log agent or an Internet of Things protocol, and labeling an event timestamp and a source identifier for each piece of data; the preprocessing standardization module is used for performing deduplication, cleaning, desensitization and dimension table association on the collected data and outputting a unified event structure; the stream-oriented computing module is used for executing window aggregation, state updating and complex event processing under event time semantics and supporting water level management and just one-time semantic processing, high-timeliness and consistent monitoring is achieved through self-adaptive water level, double-layer windows and dynamic threshold gating fusion, versioning playback and approximate computing cost reduction are supported, and the method is suitable for large-scale popularization and application. And the system has automatic degradation and self-healing capabilities.

The invention relates to the field of dynamic jump behavior simulation analysis of a thin-wall arch structure, in particular to a thin-wall arch structure finite element approximate calculation method and a lightweight system. The invention particularly provides a thin-wall arch structure finite element approximate calculation method and a lightweight system, and the method comprises the steps: carrying out one-time quasi-static equilibrium path analysis, obtaining a characteristic value closest to zero of each increment step, recognizing characteristic values before and after sign change, carrying out two-time perturbation finite element analysis, and carrying out two-time perturbation finite element analysis; the method comprises the following steps of: obtaining an approximate transient dynamic jump parameter and a feature vector, obtaining an approximate jump parameter and a feature vector at a saddle point based on a feature value interpolation closest to zero, finally obtaining an approximate transient jump response through a Gaussian hyper-geometric function, and proposing a Python / C-based hybrid programming method to realize the lightweight of a finite element analysis system. And the calculation cost and the analysis difficulty of the flexible shallow arch saddle point transient jump analysis can be effectively reduced.

The invention provides a computing device and method based on RISC-V extension instructions, the computing device supports approximate computation of mixed precision according to approximate computation instructions in an extended approximate computation instruction set, and the computing device comprises an out-of-order scheduling and register reading module used for executing instruction dependency analysis and operand preloading, scheduling the non-approximate calculation instruction and the approximate calculation instruction to different transmitting queues respectively; the first instruction transmitting queue is used for temporarily storing a to-be-transmitted non-approximate calculation instruction; the second instruction transmitting queue is used for temporarily storing approximate calculation instructions to be transmitted; the precise calculation module is used for completing precise calculation related tasks according to the instruction from the first instruction transmitting queue; and the approximate calculation module is used for completing approximate calculation related tasks according to the instructions from the second instruction transmitting queue, and supports approximate calculation of various precisions.

The invention discloses an all-digital calibration method applied to sampling time mismatch of a time-interleaved ADC, and belongs to the field of ADC sampling clock skew calibration. According to the method, digital codes of two adjacent channels are extracted to obtain autocorrelation functions of the two channels, and the autocorrelation functions of the adjacent channels are subtracted and then are subjected to Taylor expansion, so that the sampling time mismatch of the two channels is obtained; obtaining the product of the clock skew term and the derivative of the autocorrelation function; and on the basis of a bilateral approximation principle, approximate calculation is performed on the derivative of the autocorrelation function to obtain a more accurate derivative of the autocorrelation function, so that the value of a clock skew item of each channel is obtained, and a real clock skew variable is obtained through matrix operation to calibrate the digital code of the multi-channel ADC. Compared with the prior art, the method provided by the invention can realize digital calibration with higher precision and higher bandwidth. In a multichannel time interleaving application scene with harsh requirements on calibration precision and calibration bandwidth, the method has remarkable advantages.

A computing method based on a smart contract, wherein a smart contract for performing approximate computing is deployed on a blockchain, comprising: receiving a smart contract call transaction initiated by a computing initiator for the smart contract; the smart contract call transaction includes computing parameters corresponding to the approximate computing; the computing parameters include a data identifier of a data set participating in the approximate computing; in response to the smart contract call transaction, calling sampling logic contained in the smart contract call transaction, dividing the data set corresponding to the data identifier into an outlier data subset consisting of a plurality of outlier data samples and a non-outlier data subset consisting of a plurality of non-outlier data samples, and sampling non-outlier data samples in the non-outlier data subset; calling the computing logic contained in the smart contract call transaction, performing precise computing on the outlier data samples in the outlier data subset, performing approximate computing on the sampled non-outlier data samples, and merging the results of the precise computing and the approximate computing.

The application relates to a real-valued super-resolution direction estimation method of a high-order acoustic field sensor array, which uses a received signal covariance matrix to approximately calculate an estimated value of noise power, avoids the iterative operation process of noise power in the prior art, improves the calculation efficiency, and reduces the floating-point operation amount. By constructing an augmented matrix, the array receiving data matrix and the array manifold matrix with a multi-dimensional structure of an element are made into Hermitian matrices, so that the unitary transformation processing of the related parameters of the high-order acoustic field sensor array is realized. On the basis of obtaining the array receiving data matrix and the array manifold matrix in the real number domain, the array receiving data matrix and the array manifold matrix are applied to a sparse approximate minimum variance method with a variable exponential factor, and the completely real-valued sparse approximate minimum variance direction estimation with a variable exponential factor is realized.

This invention relates to the fields of high-speed serial communication and digital signal processing, and discloses a low-power approximate equalization circuit and method based on frequency domain error attribute mapping. The circuit includes: a Fast Fourier Transform (FFT) module for converting the time-domain signal to be equalized into a frequency-domain signal; a frequency-domain equalization processing module for equalizing the frequency-domain signal; an Inverse Fast Fourier Transform (IFT) module for converting the equalized frequency-domain signal into a time-domain output signal; and a mapping control module for constructing a three-dimensional error attribute mapping relationship with frequency domain sub-bands as the first dimension, approximate calculation accuracy level as the second dimension, and the error polarity of the approximate arithmetic unit as the third dimension. This invention simultaneously considers frequency domain position, approximate accuracy, and error polarity characteristics in frequency-domain equalization, and achieves system-level error balance without introducing additional compensation circuits, thereby achieving low-power, high-reliability frequency-domain equalization.

The application discloses a heterogeneous platform approximate computing task optimization mapping method based on DVFS and DPM. Firstly, real-time tasks with correlation are modeled as an approximate computing task model, so that a task directed acyclic graph (DAG), a task correlation matrix and a six-tuple representing task characteristics can be obtained; then, a mechanism of DVFS and DPM combination is introduced based on a heterogeneous multi-core platform; a problem description of task mapping based on QoS and energy joint optimization is constructed; a variable substitution method and a Big-M reconstruction method are used to process nonlinear terms in the problem, the task mapping problem is linearized, and an optimal solution is obtained through a Gurobi solver; a task layering method and a greedy algorithm are used to design a low-complexity heuristic algorithm, and the scalability of the mapping method is improved. The method of the application adopts the mechanism of DVFS+DPM joint optimization under the premise of meeting the system real-time, energy efficiency and reliability constraints, and improves the QoS of the system.

The invention relates to a hierarchical multi-objective optimization method and system for approximate calculation parameter optimization. The method comprises the following steps: constructing a hierarchical search model for approximate calculation commitment optimization; and in the category-type decision-making layer, taking each approximation strategy as an arm, maintaining the arms by adopting a multi-arm tiger machine algorithm, obtaining random sampling values in each round of iteration according to the obtained Beta distribution, and evaluating the target arm corresponding to the maximum value so as to obtain an arm to be optimized. And inputting the parameter point to be evaluated into a numerical decision-making layer to perform parameter iterative optimization, and generating a next parameter point to be evaluated by maximizing a qNEHVI acquisition function, so that a program, corresponding to the parameter point, of the arm to be optimized is executed through a multi-target Bayesian optimization engine, and an optimization evaluation result is obtained. And obtaining the most approximate calculation configuration according to the result and the preset evaluation budget. The method can face mixed and hierarchically dependent variable space, and can improve the tuning efficiency and reduce the cost.

The application discloses an aging-aware precision reconfigurable logic synthesis method and system, and belongs to the technical field of integrated circuit EDA. The application aims to solve the problems of limited optimization space, introduced error from the beginning and lack of aging modeling in the existing aging-aware synthesis. The application constructs an aging standard cell library, iteratively applies constant replacement to the original circuit to generate multiple approximate candidate circuits, and then constructs a precision reconfigurable circuit composed of reconfigurable modules, which dynamically switches between accurate mode and approximate mode. Through aging-aware timing modeling, a power function model of gate delay with running time is established, and the aging continuity during mode switching is processed. The accurate mode life and the approximate mode remaining life are predicted, and the circuit with the highest score is automatically selected according to the score function. The application can improve the circuit life by about 9.5 times with an additional area overhead of about 3.72% under the premise of meeting the error constraint, which significantly enhances the long-term reliability of digital circuits.

The application belongs to the technical field of permanent magnet magnetic drive, and provides a permanent magnet coupling centering state prediction method based on time sequence signals. First, two mutually orthogonal state vectors are introduced to represent the eccentricity and position angle of the inner and outer rotors of the permanent magnet coupling, and the axial section of the inner and outer rotors of the permanent magnet coupling is theoretically modeled; in combination with the approximate calculation model of the Monte Carlo algorithm, the measured results are referenced to the calculation to reevaluate the weight of the data set, and the fast prediction and evaluation of the centering state of the permanent magnet coupling are realized. The application can realize the prediction and evaluation of the centering state of different types of permanent magnet couplings, and has strong adaptability; in addition, the measured data is reevaluated by the statistical probability method, the calculation result is corrected, the accuracy of the prediction value is ensured, and important technical support is provided for the multi-parameter state evaluation and prediction of the permanent magnet coupling. In the aspect of actual engineering application, it has good actual application performance, simple operation and small calculation amount.

The invention relates to a digital circuit (10) for calculating a scalar product between two vectors and . The digital circuit comprises a multiplier (11), an accumulator (12) comprising at least one adder (13) and a register (14), as well as a control circuit (15) for the accumulator. At a clock tick of index , the multiplier is configured to calculate the result of the multiplication , and the accumulator is configured to add with the current value of the register. The result of the addition is then stored in the register. The control circuit is configured to control the accumulator so as to perform the addition approximately for at least one addition among the additions of the calculation of the scalar product. The digital circuit is in particular intended to be used in an electronic device implementing a cryptographic algorithm based on a "learning with errors" (LWE) technology. Figure for the abstract: Fig. 1

The invention discloses a Bayesian learning-based tensor interpolation decomposition method and device, and the method comprises the following steps: S1, expanding a multi-order tensor into a matrix according to one dimension, carrying out the clustering of the matrix, extracting a certain number of column vectors from different clustering types, and organizing the column vectors into a skeleton matrix; s2, regarding the skeleton matrix as a factor matrix in CP decomposition, and regarding the remaining factor matrixes as weight matrixes; carrying out probability modeling on tensor interpolation decomposition by utilizing leaf bass learning, and adding prior to the tensor; s3, setting prior for the weight matrix, drawing a probability graph model according to the prior of the weight matrix, and exporting model posterior distribution; s4, using a Gibbs sampling algorithm to carry out posterior approximate calculation of the weight matrix; and S5, calculating a model error value based on the tensor approximate value, if the model error value is smaller than a set threshold value, outputting a weight matrix, and otherwise, carrying out iteration on the step S4. The method has the effect of high interpretability.

A novel and useful hybrid quantum-classical mechanism for approximating geometric entanglement of multi-qubit pure states with noise mitigation in a quantum device. The mechanism applies the Higher-Order Power Method that approximates solutions to rank-1 tensor approximation and is executed virtually solely on a quantum computer with only angle computation performed on a classical computer. The mechanism iteratively estimates a closest separable state and an estimate of the corresponding entanglement eigenvalue in a quantum system. During each iteration, the mechanism applies a special unitary operator that skips one of the qubits. The state of the skipped qubit is recovered using one-qubit tomography to obtain updated angles used for a subsequent qubit. This procedure is repeated to converge to a final entanglement eigenvalue. A depolarizing noise mitigation procedure is also provided to generate a reduced noise estimate of geometric entanglement.

One example aspect of the present disclosure is directed to a method for operating a quantum computing system (QCS). The QCS includes a quantum processor device that includes a set of qubits and a set of qubit couplers. The method includes determining a set of dressed qubit frequencies. Each dressed qubit frequency of the set of dressed qubit frequencies corresponds to a separate qubit pair of the set of qubits. A set of bare qubit frequencies is generated based on the set of dressed qubit frequencies. A spin-Hamiltonian for the set of qubits is approximated based on the set of bare qubit frequencies

The invention relates to the technical field of reliability engineering, in particular to a reliability evaluation method and evaluation device for an engineering production system, and the method comprises the steps: obtaining a reliability block diagram of the engineering production system, determining the metadata of each function block, generating a reliability function network, marking a typical reliability structure unit, and obtaining a reliability function network; the method comprises the following steps: determining a function subnet, configuring a time domain strategy to generate a self-adaptive time grid, solving the equivalent reliability of the function subnet at a self-adaptive time point of the self-adaptive time grid to obtain a reliability sampling sequence of the engineering production system, and generating a reliability evaluation result. Therefore, the problems that in the related technology, due to the fact that semantic information corresponding to a reliability block diagram depends on manual disassembly, and a reliability evaluation result is calculated through fixed step size discrete approximation, missed judgment and misjudged are likely to occur due to complex topology, the calculation precision is poor in a high-risk time period, the calculation efficiency is low in a stable time period, and engineering decision is difficult to support are solved.

The present invention discloses a task offloading method and device based on approximate computing reuse in cloud-edge collaboration. Based on the cloud-edge collaboration scenario in edge computing, the method employs approximate computing reuse technology on edge nodes to reduce computational latency. The joint optimization problem of latency and energy consumption in this scenario is modeled as a MINLP (mixed integer nonlinear programming) problem. Finally, a two-stage heuristic algorithm based on the Karush-Kuhn-Tucker (KKT) condition and greedy thinking is designed. By rationally planning offloading decisions, reuse decisions, and computing resource allocation, the combined loss of latency and energy consumption is reduced.

A computing method based on a smart contract, which is applied to a node device in a blockchain. A smart contract for performing approximate computing is deployed on the blockchain, and the method includes: receiving a smart contract call transaction initiated by a computing initiator for the smart contract; wherein the smart contract call transaction includes computing parameters corresponding to the approximate computing; the computing parameters include data identifiers of a data set participating in the approximate computing; in response to the smart contract call transaction, calling the sampling logic included in the smart contract to perform stratified sampling on data samples in the data set corresponding to the data identifiers, and further calling the approximate computing logic included in the smart contract to perform approximate computing based on the data samples obtained by stratified sampling from the data set, so as to obtain an approximate computing result for the data set.

This invention proposes a robotic arm obstacle avoidance path planning method based on an improved ant colony algorithm, relating to the fields of robot path planning and intelligent optimization algorithms. This method endows the joint configuration space with a non-uniform metric structure induced by a metric tensor G(q), where G(q) is derived from the normalized joint inertia matrix W. I The algorithm consists of three parts: the singularity gradient outer product term and the obstacle spacing gradient outer product term. Local geodesic distances are approximated using the mean of the metric tensors at both ends of the node. All edge weights are pre-calculated and cached during the PRM graph construction phase. The ant colony uses the reciprocal of the geodesic distance as a heuristic function, drives non-uniform pheromone evaporation using the normalized value of the metric tensor trace increment, and uses the weighted sum of geodesic length cost and inertia-weighted velocity mutation penalty as the comprehensive path cost. The beetle whisker algorithm performs pre-search and completes non-uniform pheromone initialization under geodesic metrics. This method effectively improves path safety, continuity, and dynamic adaptability.

A digital circuit for including a scalar product between two vectors (a0, a1, . . . , ai, . . . , aN-1) and (s0, s1, . . . , si, . . . , sN-1). The digital circuit includes a multiplier, an accumulator including at least one adder and a register, as well as a control circuit of the accumulator. At a clock tick of index i, the multiplier is configured to compute the result ri of the multiplication ai×si, and the accumulator is configured to add ri with the current value of the register. Afterwards, the result of the addition is memorised in the register. The control circuit is configured to control the accumulator so as to perform the addition in an approximate manner for at least one addition amongst the N additions of the computation of the scalar product. In particular, the digital circuit is intended to be used in an electronic device implementing a cryptographic algorithm based on a “Learning With Errors” (LWE) technology.

The application provides a maximum and minimum value function processing method and system and a storage medium, which are characterized by the following steps: S1-1, obtaining a maximum and minimum value function and first and second ciphertexts to be compared; S1-2, summing the first and second ciphertexts based on a homomorphic encryption algorithm to obtain a first result; S1-3, calculating a second result obtained by dividing the first result by 2 based on a predetermined homomorphic division operation rule; S1-4, performing square root on the square of the difference between the first and second ciphertexts based on a predetermined square root approximation operation rule to obtain an approximate third result; S1-5, calculating a fourth result obtained by dividing the third result by 2 based on the predetermined homomorphic division operation rule; S1-6, performing corresponding homomorphic encryption processing on the second and fourth results according to the type of the maximum and minimum value function to obtain a fifth result; and S1-7, decrypting to obtain the processing result of the maximum and minimum value function.

The present invention discloses a precision-configurable multiply-accumulate unit designed for a neural network accelerator. First, the zero-th computing unit and the first computing unit are summed through a fifth summation module, then the second computing unit and the third computing unit are summed through a sixth summation module, and finally the parts generated by the above two summations are finally summed through a third summation module. All the summation modules in the precision-configurable multiply-accumulate unit are correspondingly turned off according to different input bit widths to adapt to the multiply-accumulate operations of each layer of convolutional neural networks with different bit widths of 2 bits, 4 bits, and 8 bits. While ensuring a certain precision of the CNN, they not only simplify the computing unit and the external complex configurable logic, but also introduce the concept of approximate computing. Approximate computing is introduced into the configurable computing unit for the first time, enabling the architecture to further reduce power consumption based on bit-level flexibility and adapt to parameters from different quantization methods of the network.

A method of analyzing a particular computing product, including: receiving a plurality of images of a particular layout of the particular computing product; segmenting, using a classification model, the plurality of images to identify computing components of the particular computing product; analyzing the particular layout, including, for each computing component of the particular layout: approximating a physical size of the computing component; identifying a predetermined layout weight of the computing component; determining a proximity of the component to each other computing component; calculating a computing component score for the computing component for the particular layout based on i) the physical size of the computing component, ii) the predetermined layout weight of the computing component, and iii) the proximity of the computing component to each other computing component; and determining a layout score of the particular layout based on the computing component score of each of the computing components.

The application discloses an improved model-free current prediction control method and device and system based on a forgetting factor. The method does not need to acquire system parameters in advance, only needs to collect a load current, and then approximately calculates a current increment from historical current data, and then outputs an optimal inverter switch state from a minimized current value function, and meanwhile, a forgetting factor is introduced to weaken the adverse effect of a sampling error on the system, so that the model-free current prediction control is realized. On the basis of guaranteeing the realization of the parameter-free control, the forgetting factor is introduced to weaken the adverse effect of the sampling error on the system, the current quality is improved while the response speed is faster, and the robustness of the control is improved. The application is suitable for different types of power electronic topological structures, and does not need to separately perform mathematical modeling on different types of power electronic topological structures, has a reference significance for the model-free prediction current control of the power electronic converter, and has a wide application prospect.

The embodiment of the invention provides a nonlinear operator approximate calculation device and method, a neural network processor and a medium, and belongs to the technical field of neural networks. The device comprises: a floating point number evaluation unit receiving original floating point data of an original neural network operator, and performing compensation interval evaluation on the original floating point data according to a preset floating point value domain range to obtain compensation interval evaluation information; if the compensation interval evaluation information represents that the original floating point data is not in the preset floating point value domain range, the index splitting unit splits the original floating point data into a first floating point number and a second floating point number; the operation compensation unit performs fitting compensation on the first floating-point number to obtain first output data; and the splicing unit splices the first output data and the second floating-point number passing through the original neural network operator to obtain target output data. According to the invention, the computing resources and time of a computer system can be reduced, the full-value-domain compensation of the neural network operator is completed with few hardware resources, the computing precision is improved, and the reasonability of network reasoning is ensured.