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Structure and circuit of logarithmic skip adder

A circuit structure, adder technology, applied in circuits, instruments, electrical components, etc.

Inactive Publication Date: 2004-09-01
PEKING UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Either solution requires an additional level of logic delay on the critical path

Method used

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  • Structure and circuit of logarithmic skip adder
  • Structure and circuit of logarithmic skip adder
  • Structure and circuit of logarithmic skip adder

Examples

Experimental program
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Embodiment Construction

[0080] A further description will be given below in conjunction with embodiments.

[0081] figure 1 It is a 32-bit adder structure. This structure divides the 32 bits into 5 groups. The carry jump algorithm is used between the groups, and the ELM tree addition structure is used in the group to make the carry transfer within the group parallel. The logic level of the critical path and the number of bits in the group are logarithmic relationship. This overcomes the speed limitation caused by the serial carry in the traditional carry skip adder group. The ELM structure of each group is as figure 2 , image 3 , Figure 4 , Figure 5 Shown.

[0082] Compared with other tree structures, the ELM adder embeds the summation logic into the tree structure, so that after getting the previous stage carry, only one logic gate delay is required to obtain the sum of each bit and the next stage carry. For other tree structures, the local carry must be obtained first, and then the local sum is c...

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PUM

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Abstract

The invention relates to a circuit of digital adder in binary. The carry skipping algorithm is used between grups and the ELM tree type adding structure is used inside group in the circuit. Adopting new carry combination structure makes the initial carry embed into the carry chain so as to realize transferring parallel carry within group. The relationship between the delay of key path and number of bits within group is logarithmic. The invented circuit structure has advantages of the adder produced with small area and quick speed, simple connecting wire, easy to be integrated. The invention can implement binary add operation in 32 bits and 16 bits effectively.

Description

Technical field: [0001] The invention relates to the field of integrated circuit design, in particular to a 32-bit adder circuit structure. Background technique: [0002] Binary addition is the most complicated operation in the microprocessor ALU (arithmetic logic unit), and it is the key to determining the speed of the ALU operation. Currently commonly used algorithms and structures include Carry Lookahead Adder, Carry Skip Adder, Tree-Structured Adder, such as "IEEE Transactions on Circuits and Systems-II: Analog and Digital SignalProcessing, Vol.43, No.10, October 1996, the ELM tree structure adder in "Area-Time-Power Tradeoffs in ParallelAdders". The advance bit adder is faster, but the hardware overhead is large; carry skip The structure saves area, but the speed is limited, and it is not suitable for addition operations of 16 bits or more; while the tree adder has defects in fan-out or wiring complexity. Common circuit implementations include static, dynamic, asynchronous a...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F7/00H01L21/70H01L27/00
Inventor 吉利久贾嵩王迎春刘凌兰景宏张钢刚傅一玲
Owner PEKING UNIV
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