High-performance approximate full adder gate-level unit

A full adder, high-performance technology, applied in the field of high-performance approximate full adder gate-level units, can solve the problems of large area occupied by hardware circuits, large power consumption, etc., and achieve fast speed, low power consumption, and small area Effect

Active Publication Date: 2020-06-19
NANJING UNIV OF AERONAUTICS & ASTRONAUTICS
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  • Abstract
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  • Claims
  • Application Information

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Problems solved by technology

[0004] The existing full adder uses more gate circuits, and the corresponding transistors are als

Method used

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  • High-performance approximate full adder gate-level unit
  • High-performance approximate full adder gate-level unit
  • High-performance approximate full adder gate-level unit

Examples

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Embodiment

[0019] Example: such as figure 1 Shown is the structural diagram of the high-performance approximate full adder gate-level unit of the present invention, comprising: the first NOR gate, the second NOR gate, the third NOR gate and the NOT gate; the first NOR gate of the first NOR gate One input end is the addend input end, the second input end is the summand input end, the output end connects the first input end of the second NOR gate and the first input end of the third NOR gate; the second NOR gate The second input terminal of is the low carry input terminal, and the low carry input terminal is connected with the high carry output terminal of the previous gate level unit in the approximate full adder constituted by the gate level unit, the second NOR gate The output end of the NOR gate is the sum output end of this gate-level unit; the second input end of the second NOR gate is also connected with the input end of the NOR gate, and the output end of the NOR gate is connected ...

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Abstract

The invention discloses a high-performance approximate full adder gate-level unit, which comprises a first NOR gate, a second NOR gate, a third NOR gate and a NOT gate, the first input end of the first NOR gate is an addend input end, the second input end is an addend input end, and the output end is connected with the first input end of the second NOR gate and the first input end of the third NORgate; the second input end of the second NOR gate is a low carry input end, and the output end of the second NOR gate is the sum output end of the gate-level unit; the second input end of the secondNOR gate is further connected with the input end of the NOT gate, the output end of the NOT gate is connected with the second input end of the third NOR gate, and the output end of the third NOR gateis the high carry output end of the gate-level unit. Compared with an accurate full adder, the full adder has the advantages that the performance is improved by 50 percent in the aspect of key path delay, and the circuit complexity is reduced by 58 percent.

Description

technical field [0001] The invention relates to the field of approximate circuit design, in particular to a high-performance approximate full adder gate-level unit. Background technique [0002] With the continuous enrichment and development of the functional experience of various mobile device terminals, power consumption has become a key issue restricting the development of digital integrated circuit design. The industry's requirements for chip design have changed from pursuing high performance and small area to comprehensive requirements for performance, area and power consumption. Therefore, how to reduce the power consumption of digital integrated circuits under the premise of ensuring reliable circuit performance has become a research focus in academia and industry. [0003] A large number of studies have shown that the calculation accuracy of digital integrated circuits is directly proportional to power consumption. Reducing calculation accuracy can achieve the effec...

Claims

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Application Information

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IPC IPC(8): H03K19/21H03K19/00G06F7/501
CPCH03K19/215H03K19/0013G06F7/501
Inventor 刘伟强哈伦·瓦里斯袁田王成华
Owner NANJING UNIV OF AERONAUTICS & ASTRONAUTICS
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