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A technology of multipliers and binary multipliers, applied in the fields of instruments, electrical digital data processing, digital data processing components, etc., can solve the problems of low speed and resource consumption, and achieve the effect of improving operation speed and reducing resource consumption.
Inactive Publication Date: 2013-02-13
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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[0006] The purpose of the invention is in order to solve the existing mold-oriented (2 ...
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[0024] The present invention will be further elaborated below in conjunction with the accompanying drawings and specific embodiments.
[0025] The mold of the present invention (2 n +3) The multiplier structure is as follows figure 1 As shown, among them, 1 is the n+1 binary multiplier, 2 is the n-bit inverter array, 3 is the n-bit CSA compressor array, 4 is the first 1-bit inverter, and 5 is the first n-bit binary Adder, 6 is a 1-bit full adder, 7 is the second 1-bit inverter, 8 is a 5-bit adder, 9 is the second n-bit binary adder, 10 is the third 1-bit inverter, 11 is The third n-bit binary adder, A[n:0] and B[n:0] are the inputs of the n+1-bit binary multiplier 1, and P[2n+1:0] is the n+1-bit binary multiplier 1 output; P[2n-1:n] is the input of n-bit inverter array 2, is the output of n-bit inverter array 2; and P[n-1:0] are the input of n-bit CSA compressor array 3, L[n-1:0] and H[n-1:0] are the output of n-bit CSA compressor array 3; H[ n-1] is the input of 1-bi...
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Abstract
The invention discloses a modular multiplier, which comprises (n+1)-bit binary multiplier, an n-bit inverter array, an n-bit CSA compressor array, a first n-bit binary adder, a 1-bit full adder, a 5-bit adder, a first 1-bit inverter, a second 1-bit inverter, a third 1-bit inverter, a second n-bit binary adder and a third n-bit binary adder. According to a modular (2n+3) multiplier, the result of binary multiplication serves as an operation number and is reprocessed, so that repeated correction of the traditional modular (2n+3) multiplier is changed into one-step correction, the resource consumption of the modular (2n+3) multiplier is greatly reduced, and the operation speed is improved.
Description
technical field [0001] The invention belongs to the field of computers and integrated circuits, and in particular relates to the design of a high-speed multiplier. Background technique [0002] Before introducing the multiplier, first explain the Residue Number Systems (RNS, Residue Number Systems). The remainder system RNS is a numerical representation system that describes numbers through the remainder of a set of pairwise coprime remainder bases. by {m 1 ,m 2 ,...,m L} composed of L remainder bases, integer X, 0≤X<M, where M=m 1 ×m 2 ×…×m L , there is a unique representation in the RNS system as X={x 1 ,x 2 ,...,x L}, in Denotes X for modulo m i remainder of . To operate on two operands in the remainder system, the operator is Θ, which can be defined as: [0003] {z 1 ,z 2 ,…,z L}={x 1 ,x 2 ,...,x L}Θ{y 1 ,y 2 ,...,y L},in Here Θ can be modular addition, modular subtraction or modular multiplication. In a remainder system these arithmetic op...
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