High-frequency clock frequency detection structure for resisting attack chip

A high-frequency clock and frequency detection technology, applied in the monitoring of pulse chain mode, platform integrity maintenance, etc., to achieve the effects of insensitivity to process errors, reduced system power consumption, and small layout area

Active Publication Date: 2016-12-07
TIANJIN UNIV
View PDF6 Cites 9 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] 1. Yi Qingsong, Dai Zibin; SoC Security Chip Physical Level Attack Methods

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • High-frequency clock frequency detection structure for resisting attack chip
  • High-frequency clock frequency detection structure for resisting attack chip
  • High-frequency clock frequency detection structure for resisting attack chip

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0021] The technical solution of the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments, and the described specific embodiments are only for explaining the present invention, and are not intended to limit the present invention.

[0022] Aiming at the problem that anti-attack chips are vulnerable to frequency attacks, the present invention proposes a frequency measurement circuit for externally input high-frequency clocks. The circuit effectively uses the internal low-frequency clock as a counting gate to count the number of high-frequency clock cycles within a fixed time , thus pushing the high-frequency clock frequency. When the obtained frequency exceeds the normal operating frequency range, an alarm signal is generated.

[0023] A kind of high-frequency clock frequency detection structural circuit for the anti-attack chip proposed by the present invention, a technical scheme of its implementatio...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention discloses a high-frequency clock frequency detection structure circuit for resisting an attack chip. The circuit comprises two D triggers which are connected in series and are triggered by a rising edge, three two-input AND gate, a delay unit D, an OR gate, a 10-bit asynchronous reset binary addition counter CT, a 10-bit latch and a 10-bit digital comparer DCMP. The two D triggers which are triggered by the rising edge, and the three two-input AND gate form a gate control clock structure. The delay unit D is formed by connecting the even number of phase inverters in series. Delay time is controlled by adjusting the number of the phase inverters. Two 10-bit registers, a frequency upper limit register H and a frequency lower limit register L, are contained in the10-bit digital comparer DCMP. The delay unit D or the OR gate forms a delay reset structure. An internal low-frequency clock is taken as a counting gate, the number of high-frequency clock periods is counted in fixed time, and the high-frequency clock frequency is deduced. When the obtained frequency exceeds a normal working frequency range, an alarm signal is generated.

Description

technical field [0001] The invention relates to the field of chip anti-attack, in particular to an external high-frequency clock frequency detection structure using an internal low-frequency clock as a counting threshold. Background technique [0002] In recent years, attack methods against various information systems and chips have been continuously proposed, which seriously threatens information security. With the advancement of microelectronics technology, the anti-attack technology for different attack methods is also constantly developing. Compared with software protection, the security protection technology based on the underlying hardware circuit has a higher security level, and has gradually become the first choice for information systems and chips to resist attacks. [0003] Some information security chips need to work under the drive of an external input clock, and the working speed of the internal circuit is completely determined by the clock. An attacker can at...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
IPC IPC(8): H03K5/19G06F21/55
CPCG06F21/55H03K5/19
Inventor 赵毅强辛睿山王佳李跃辉章建成
Owner TIANJIN UNIV
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products