17 results about "Gate effect" patented technology

This invention discloses a negative voltage generation circuit, PCB board, and controller, including a first N-type power transistor MDN1, a charging unit, a negative voltage output switching unit, a substrate modulation unit, and a timing control unit. The source of the first N-type power transistor MDN1 is grounded, and the drain of the first N-type power transistor MDN1 is connected to the output terminal of the charging unit and the input terminal of the negative voltage output switching unit. The gate and substrate of the first N-type power transistor MDN1 are respectively connected to the substrate modulation unit. The timing control unit is connected to the charging unit, the negative voltage output switching unit, and the substrate modulation unit. The substrate modulation unit is used to track and modulate the gate potential and substrate potential of the first N-type power transistor MDN1 to eliminate the potential difference between the gate potential and the substrate potential. By eliminating the back gate effect of the NMOS power transistor through bootstrap substrate modulation, the negative voltage conversion efficiency of the charge pump is greatly improved, which is suitable for low-power, high-performance, and high-efficiency negative voltage output scenarios.

Methods and structures are presented for mitigating back-gating effects in radio frequency (RF) silicon-on-insulator (SOI) substrates, RF-SOI. According to an aspect, a first implant or junction is formed in a region of a trap-rich layer (TRL) of the RF-SOI beneath a first circuit / device to be protected. The first implant or junction is entirely contained within the TRL. A planar surface area of the first implant and / or junction entirely contains a projection of a planar surface area of the first circuit and / or device. The first implant or junction is biased via a through-BOX contact (TBC) that penetrates a BOX layer at a shallow trench isolation region formed in the RF-SOI. According to another aspect, a second implant or junction is formed in a region of the TRL beneath a second circuit / device. The first implant or junction and the second implant or junction are not connected and are separated by an undoped region of the TRL.

The application relates to a field effect transistor and a power electronic system. The field effect transistor comprises a substrate, a channel layer formed on the substrate, a barrier layer formed on the channel layer, a two-dimensional electron gas channel formed between the barrier layer and the channel layer, a source electrode, a gate electrode and a drain electrode formed on the barrier layer and arranged in sequence at intervals along a first direction, a P-type compensation island at least partially higher than the barrier layer and located between the gate electrode and the drain electrode, the P-type compensation island being spaced apart from the drain electrode and the gate electrode, a shielding plate located above the P-type compensation island, a passivation layer arranged between the shielding plate and the P-type compensation island, and the shielding plate being arranged at intervals from the gate electrode and the drain electrode. Through the coupling effect of the P-type compensation island and the shielding plate, the potential distribution between the gate electrode and the drain electrode is more uniform, thereby reducing the peak value of the high field on the drain side, improving the breakdown margin, and effectively reducing the virtual gate effect caused by electron capture after high-voltage turn-off, thereby greatly reducing the increase of the dynamic on-resistance.

The invention discloses a gate structure based on an array p-GaN layer embedded MIS and a semiconductor power device, the gate structure is arranged on the surface of an AlGaN barrier potential layer, and comprises a continuous p-GaN layer, a gate sinking metal and an interval p-GaN layer which are sequentially arranged on the surface of the AlGaN barrier potential layer along the transverse direction; the continuous p-GaN layer is close to the source electrode, and the interval p-GaN layer is close to the drain electrode; wherein the interval p-GaN layer is divided into a plurality of segments at equal intervals along the longitudinal direction by the bulges on the surface of the gate sinking metal; the semiconductor power device comprises a substrate, a nucleating layer, an AlGaN transition layer with gradually-changed Al components, a GaN buffer layer, an AlGaN back barrier layer, a UID GaN layer and an AlGaN barrier layer which are sequentially covered from top to bottom, and the gate structure is installed on the AlGaN barrier layer. According to the gate structure, the dynamic threshold voltage drift caused by the gate-drain coupling barrier lowering effect is reduced, and the problem that the dynamic on-resistance is increased in the switching process caused by the back gate effect is inhibited; the problem of electric field concentration below the grid electrode is optimized, the voltage resistance of the device is improved, and the leakage current of the grid electrode is reduced.

An electronic device includes an one of aluminum gallium nitride, aluminum nitride, indium aluminum nitride, or indium aluminum gallium nitride back barrier layer over a buffer structure, a gallium nitride layer over the back barrier layer, a hetero-epitaxy structure over the gallium nitride layer, first and second transistors over the hetero-epitaxy structure, and a hole injector having a doped gallium nitride structure over the hetero-epitaxy structure and a conductive structure partially over the doped gallium nitride structure to inject holes to form a hole layer proximate an interface of the back barrier layer and the buffer structure to mitigate vertical electric field back gating effects for the first transistor.

This invention provides a radiation-resistant GaN logic circuit structure and its fabrication method, belonging to the field of semiconductor technology. The circuit structure includes, from bottom to top, a substrate layer, an aluminum nitride nucleation layer, a gallium nitride buffer layer, an aluminum gallium nitride polarization-induced hole transport layer, a gallium nitride channel layer, and a barrier layer. The device has an electrically connected 2DEG resistive region and an enhancement-mode Schottky gate GaN HEMT region. On the surface of the enhancement-mode Schottky gate GaN HEMT region, a drain ohmic electrode, a gate ohmic electrode, a source ohmic electrode, and a HEMT-side deep trench electrode are spaced apart along the source-drain direction. A resistive-side deep trench electrode connected to the gallium nitride buffer layer is disposed on the surface of the 2DEG resistive region, and the resistive-side deep trench electrode and the HEMT-side deep trench electrode are bridged. This effectively prevents hole accumulation at the bottom of the active region, alleviates threshold drift caused by the back-gate effect and fluctuations in the 2DEG resistance, and improves the device's resistance to single-event burn-out.

The invention discloses a gallium nitride power device and a preparation method of the gallium nitride power device. The gallium nitride power device comprises a substrate; the buffer layer is arranged on one side of the substrate; the channel layer is arranged on the side, away from the substrate, of the buffer layer; the barrier layer is arranged on the side, away from the buffer layer, of the channel layer, and the barrier layer and the channel layer can generate two-dimensional electron gas; the gate structure, the source electrode and the drain electrode are arranged on the side, away from the channel layer, of the barrier layer at intervals, and the source electrode and the drain electrode are located on the two sides of the gate structure; wherein the barrier layer between the gate structure and the drain is provided with a first hollow part, the thickness of the first hollow part is the same as that of the barrier layer, and the first hollow part is etched between the gate and the drain of the barrier layer, so that the current leakage between the gate and the drain can be effectively inhibited, the virtual gate effect is relieved, and the reliability of the device is improved. Current collapse caused by 2DEG electrons captured by an AlGaN barrier layer and a surface defect trap and a channel hot electron effect is improved, and the voltage withstanding performance and the reliability of the device are improved.

One embodiment provides a gallium nitride device comprising: a silicon substrate; a channel forming layer disposed on the silicon substrate and formed as a gallium nitride (GaN)-based semiconductor layer to create a current path and induce an electron channel; a gate control layer disposed on the channel forming layer to control channel conductance by transferring a gate potential; and a gate electrode disposed on the gate control layer, wherein a bias voltage is directly applied to the silicon substrate through the channel forming layer.

The invention discloses an anti-radiation trench gate SOI LDMOS device structure, and belongs to the technical field of power semiconductors. The structure comprises a substrate, a buried oxide layer (BOX), a P buried layer, a drift region, a top Ptop region, a body region, a body contact region, a source region, a drain region and a trench gate structure. According to the structure, the P buried layer is arranged above the BOX, the back gate effect under the effect of total dose radiation is effectively restrained, threshold voltage drift and increase of leakage current are reduced, meanwhile, RESURF is formed by the P buried layer and the Ptop region at the top, and the device is kept to have good low-loss performance. The top highly-doped Ptop region can be used as an effective discharge channel of hole current after single-particle incidence, and risks of body region barrier lifting and parasitic triode triggering are reduced, so that the single-particle resistance of the device is enhanced, and the overall anti-radiation hardening level is improved. The method is suitable for high-reliability power electronics such as aerospace, satellite power management and military electronic systems.

The invention relates to the technical field of GaN-based high electron mobility transistor preparation, in particular to a double-channel GaN HEMT device and a preparation method thereof, and the device comprises a substrate, a buffer layer, a first channel layer, a first barrier layer, a second channel layer, a second barrier layer, a P-GaN epitaxial layer and a grid electrode which are sequentially stacked. Heterojunctions are respectively formed between the first channel layer and the first barrier layer and between the second channel layer and the second barrier layer, and two-dimensional electron gas is formed. By introducing the lower-layer two-dimensional electron gas channel decoupled from the upper channel, the shielding back gate effect is realized, the crosstalk effect introduced by the back gate and the trap effect of the buffer layer are further shielded, the dynamic conduction characteristic of the device is optimized, and the power loss in the switching process is reduced. In addition, the lower layer barrier can effectively reduce the problem of device breakdown caused by overlarge electric leakage of the buffer layer. Therefore, a shielding back gate effect and a buffer layer trap effect can be realized at the same time, and the method has important value for the development of a GaN-based integrated circuit.

Embodiments of the present application provide a switch array and a manufacturing method thereof, and a DC-DC switching conversion circuit using the switch array. The switch array comprises, for example, a substrate, an insulating layer and a plurality of semiconductor switching devices, the plurality of semiconductor switching devices are arranged side by side on the substrate, and the insulating layer is arranged between the substrate and the plurality of semiconductor switching devices and separates the plurality of semiconductor switching devices from each other. Each of the semiconductor switching devices comprises a barrier layer, a channel layer, a first electrode, a second electrode and a gate structure; the first electrode metal layer of the first electrode and the second electrode metal layer of the second electrode are respectively separated from the substrate by the insulating layer, so that the back gate effect problem caused by the substrate voltage bias in the related art can be overcome, and the switching performance of the device can be improved.

The invention discloses a simulation analysis method for a current collapse effect of a p-type gate GaN HEMT device under high pressure stress. The method comprises the following steps: firstly, constructing a two-dimensional model based on device process parameters, carrying out fine grid division, calibrating an electrical characteristic model through TCAD simulation, setting an acceptor type body trap on a buffer layer, and setting an acceptor type interface trap on an interface; a time model is introduced to dynamically apply bias voltage, the constant voltage of the grid electrode is 3V, the voltage of the drain electrode is 5V for 1ms, then the voltage of the drain electrode is 25V for 1ms, and then the drain electrode is recovered to 5V, and time-domain characteristics of drain electrode current are obtained through simulation; through combination of electron concentration distribution, a conduction band energy diagram and 2DEG electron concentration change, a degradation mechanism of current collapse caused by a virtual gate effect formed by the fact that electrons break away from a heterojunction potential well and enter a buffer layer under high pressure stress is disclosed. According to the method, the current collapse effect is dynamically analyzed from the microcosmic physical process, and an accurate basis is provided for reliability evaluation of the device.

The invention provides a semiconductor device radio frequency modeling method and model for a silicon-on-insulator (SOI) platform. The method comprises the following steps: constructing an equivalent circuit model comprising a gate / body end parasitic impedance network, an intrinsic capacitance module, a body resistance module and a substrate network module; an intrinsic capacitance parameter is extracted through a low-frequency CV test, Cg is decomposed into overlapping capacitance, depletion capacitance and accumulation capacitance, and a hyperbolic tangent function and polynomial correction are introduced; extracting parasitic resistance inductance by using layout information and square resistance; bulk resistance parameters modulated by voltage are extracted based on the high-frequency S parameters, and the body resistance is fitted by adopting an exponential function. The model provided by the invention can accurately reflect the back gate effect and the bulk resistance modulation effect of the SOI device, and shows excellent fitting precision in a wide frequency band, wide voltage and wide temperature range.

According to the circuit for reducing the electric leakage of the digital circuit, the substrate voltage of a PMOS device is biased, so that the voltage of the PMOS device is higher than the voltage of a first power supply, the back gate effect is increased, so that the threshold voltage of the PMOS device is increased to reduce the electric leakage, and meanwhile, the potential of a first grounding end connected with a source electrode of an NMOS tube group is increased; the potential difference between the substrate and the source electrode of the NMOS tube group is a negative number, the threshold voltage of the NMOS tube group can also be increased, and the mode can ensure that the whole digital circuit body works in a safe voltage range and does not face the risk that the circuit is broken down.

Methods and structures for mitigating back-gate effects in a radio frequency (RF) silicon-on-insulator (SOI) substrate, RF-SOI, are presented. According to one aspect, a first implant or junction is formed in a region of a trap-rich layer (TRL) of the RF-SOI that is located below a first circuit / device to protect. The first implant or junction is fully contained within the TRL. A planar surface area of the first implant and / or junction fully contains a projection of a planar surface area of the first circuit and / or device. The first implant or junction is biased via a through BOX contact (TBC) that penetrates the BOX layer at a shallow trench isolation region formed in the RF-SOI. According to another aspect, a second implant or junction is formed in a region of the TRL below a second circuit / device. The first and second implants or junctions are disjoint and separated by an undoped region of the TRL.

The invention discloses a buffer, a circuit board and electronic equipment, and relates to the technical field of electronic circuits. In the buffer, a drain bias circuit is used for outputting first bias voltage to a drain of an input field effect transistor, so that drain voltage of the input field effect transistor follows output voltage, drain-source voltage of the input field effect transistor follows the output voltage, and the channel length modulation effect can be reduced. And the body bias circuit is used for outputting a second bias voltage to the substrate of the input field effect transistor, so that the substrate voltage of the input field effect transistor follows the output voltage, the voltage between the substrate of the input field effect transistor and the source electrode follows the output voltage, and the back gate effect can be reduced. The first current source can provide current for the input field effect transistor, and enables the input field effect transistor to operate in a saturation region. Therefore, the buffer provided by the embodiment of the invention can eliminate the channel length modulation effect and the back gate effect, thereby ensuring the linearity between the input voltage and the output voltage of the buffer.

The invention provides an anti-radiation GaN logic circuit structure and a manufacturing method thereof, and belongs to the technical field of semiconductors. The circuit structure comprises a substrate layer, an aluminum nitride nucleating layer, a gallium nitride buffer layer, an aluminum gallium nitride polarization induced hole transport layer, a gallium nitride channel layer and a barrier layer which are arranged from bottom to top, and the device is provided with a 2DEG resistance region and an enhanced Schottky gate GaN HEMT region which are electrically connected. A drain ohmic electrode, a grid electrode, a source ohmic electrode and an HEMT side deep groove electrode are arranged on the surface of the enhanced Schottky grid GaN HEMT area at intervals in the source-drain direction, a resistor side deep groove electrode connected with the gallium nitride buffer layer is arranged on the surface of the 2DEG resistor area, and the resistor side deep groove electrode is in bridge connection with the HEMT side deep groove electrode. The accumulation of holes at the bottom of the active region can be effectively prevented, the threshold drift and the fluctuation of the 2DEG resistance caused by the back gate effect are relieved, and the single event burnout resistance of the device is improved.