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63 results about "Gate effect" patented technology

“The Gate effect passes only signals whose level exceeds a user-specified threshold. In other words, a Gate effect is a device that allows us to only allow sound through that is above a certain threshold level.

Methods of fabricating silicon carbide metal-semiconductor field effect transistors

SiC MESFETs are disclosed which utilize a semi-insulating SiC substrate which substantially free of deep-level dopants. Utilization of the semi-insulating substrate may reduce back-gating effects in the MESFETs. Also provided are SiC MESFETs with a two recess gate structure. MESFETS with a selectively doped p-type buffer layer are also provided. Utilization of such a buffer layer may reduce output conductance by a factor of 3 and produce a 3 db increase in power gain over SiC MESFETs with conventional p-type buffer layers. A ground contact may also be provided to the p-type buffer layer and the p-type buffer layer may be made of two p-type layers with the layer formed on the substrate having a higher dopant concentration. SiC MESFETs according to embodiments of the present invention may also utilize chromium as a Schottky gate material. Furthermore, an oxide-nitride-oxide (ONO) passivation layer may be utilized to reduce surface effects in SiC MESFETs. Also, source and drain ohmic contacts may be formed directly on the n-type channel layer, thus, the n+ regions need not be fabricated and the steps associated with such fabrication may be eliminated from the fabrication process. Methods of fabricating such SiC MESFETs and gate structures for SiC FETs as well as passivation layers are also disclosed.
Owner:CREE INC

ECO (Engineering Change Order) optimization method of multiplier based on standard cell library extension

The invention relates to an ECO (Engineering Change Order) optimization method of a multiplier based on standard cell library extension. The traditional optimization method is limited in finite drive capability of the standard cells in the library, and cannot realize the shortest path delay. The ECO optimization method comprises the steps as follows: firstly, generating a layout of an extension unit, and characterizing the extension unit to obtain an extension unit library, wherein the characterizing the extension unit comprises characterizing the delay information, characterizing an input port capacitor, characterizing the power consumption, characterizing the area and characterizing a performance function; secondly, performing time series analysis on the multiplier to obtain a key path of the multiplier; and lastly, enabling the gate effects of all stages of the key path of the multiplier to be the same by using the extension unit library so as to obtain the shortest path delay. According to the ECO optimization method, on the premise of not remarkably increasing the design cycle, the key path of the multiplier is analyzed, the shortest path delay is realized, and the performance of the multiplier is improved; in addition, the design automation is conveniently implemented, and the ECO optimization method is also suitable for the rear-end ECO optimization of other digital systems.
Owner:ZHEJIANG UNIV

Plasma processing apparatus capable of reducing gate effect

ActiveCN104051210ADistribution regulationSolve the technical problem of uneven electric field distributionElectric discharge tubesEngineeringAluminum metal
The invention discloses a plasma processing apparatus capable of reducing a gate effect. A lifting ring that can move up and down and encircles gas spraying head is arranged in a plasma processing cavity. A metal baffle plate is fixedly arranged at one side, approaching the side wall of the processing cavity, of the lifting ring and preferably, an aluminum metal baffle plate made of the same material as that of the side wall of the processing cavity is used, so that the metal baffle plate can shield a gate opening of the side wall of the processing cavity when the lifting ring descends. Therefore, a technical problem that electrical field distribution in the processing cavity is not uniform due to the gate opening of the side wall of the processing cavity can be solved. According to the technical scheme, the structure of the apparatus is simple. On the basis of the existing lifting ring, the lifting ring and the metal baffle plate are fixedly connected by a bolt or by cutting a groove for embedding the metal baffle plate in one side, approaching the side wall of the processing cavity, of the lifting ring. On the basis of the simple structure, the electric field distribution at the gate opening can be effectively adjusted, thereby effectively adjusting the electric field distribution uniformity in the processing cavity.
Owner:ADVANCED MICRO FAB EQUIP INC CHINA

Common-source common-gate amplifier and common-emitter common-gate amplifier

The present invention discloses a common-source (common-emitter) common-gate amplifier. The common-source (common-emitter) common-gate amplifier comprises a common-source (common-emitter) transistor, a common-gate transistor, an output load and a substrate biasing circuit. The common-source (common-emitter) transistor receives an input signal. The common-gate transistor sends an output signal and is connected to the output load. The amplifier has a substrate end to which the substrate biasing circuit is connected. As compared with the prior art, the present invention realizes a common-source (common-emitter) common-gate amplifier circuit with a separately biased substrate. The back-gate effect of a common-gate device is eliminated so as to improve the amplifier gain, and a direct connection between a source of the common-gate device and the substrate is also avoided so as to increase parasitic capacitance Cgb from the substrate to the gate, thereby improving the bandwidth and the gain of the amplifier. In addition, since the present invention introduces a reconfigurable biasing circuit, the linearity/noise/stray properties of a signal processing channel are balanced during the circuit switching, a good balance between flexibility and complexity is achieved, and significant improvements are made to the power consumption and area.
Owner:GUANGZHOU YIXIN INFORMATION TECH CO LTD

HEMT device with multi-metal gate structure and preparation method thereof

The invention discloses an HEMT device with a multi-metal gate structure and a preparation method thereof. The device comprises an AlGaN/GaN epitaxy layer; the two ends of the upper surface of the AlGaN/GaN epitaxy layer are connected with a source electrode and a drain electrode respectively; a gate electrode is arranged between the source electrode and the drain electrode at the place close to the source electrode side; and a first layer of metal X of the gate electrode is deposited in an electron beam evaporation mode, a second layer of metal Y of the gate electrode is deposited in a magnetron sputtering mode, the work function of the second layer of metal Y of the gate electrode is higher than that of the first layer of metal X, photoetching is not needed, and a metal structure which is formed after the gate electrode is stripped and makes contact with (Al)GaN is Y/X/Y. The multi-metal gate structure is in contact with (Al)GaN, so that the electric field is redistributed, the peakvalue of the electric field at the gate edge near the drain is reduced, and the breakdown voltage of the device is improved; and meanwhile, the lower electric field peak value of the gate edge weakensgate injection electrons to form a virtual gate effect, so that current collapse of the device is reduced, and the dynamic performance of the device is improved.
Owner:ZHONGSHAN INST OF MODERN IND TECH SOUTH CHINA UNIV OF TECH +1

Silicon-on-insulator (SOI)/metal oxide semiconductor (MOS) device structure for connecting negative voltage on backgate through negative charge pump and manufacturing method

The invention relates to a silicon-on-insulator (SOI)/metal oxide semiconductor (MOS) device structure for connecting negative voltage on back gate through a negative charge pump and a manufacturing method. The manufacturing method is characterized in that the front surface of an SOI/MOS device silicon film is perforated, a contact hole runs through a buried oxide layer, and a substrate is connected to the negative charge pump on the surface of the SOI/MOS device, so that the back gate effect of the partially-use-up SOI/MOS device under the radiation condition can be improved. The basic principle for designing the SOI/MOS device structure is that a back substrate is connected with the negative voltage, so that the distribution of an electric field inside the SOI/MOS device buried oxide layer is changed so as to influence the accumulation of positive charges on the interface of the back gate under the radiation condition, and the influence of the back gate effect caused by the radiation total dose on the performance of the device can be eliminated. Due to the adoption of the method, not only is the problem that the voltage of the back substrate of the SOI/MOS device is uncertain solved, but also the additional technique reinforcement for the back gate is not required in the manufacturing process of the device, and the process steps can be simplified. The back gate is connected with the negative voltage, so that the total dose resistance of the partially-use-up SOI/MOS circuit can be improved, and the performance of other circuits on the surface is not influenced.
Owner:58TH RES INST OF CETC
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