ECO (Engineering Change Order) optimization method of multiplier based on standard cell library extension

Abstract

The invention relates to an ECO (Engineering Change Order) optimization method of a multiplier based on standard cell library extension. The traditional optimization method is limited in finite drive capability of the standard cells in the library, and cannot realize the shortest path delay. The ECO optimization method comprises the steps as follows: firstly, generating a layout of an extension unit, and characterizing the extension unit to obtain an extension unit library, wherein the characterizing the extension unit comprises characterizing the delay information, characterizing an input port capacitor, characterizing the power consumption, characterizing the area and characterizing a performance function; secondly, performing time series analysis on the multiplier to obtain a key path of the multiplier; and lastly, enabling the gate effects of all stages of the key path of the multiplier to be the same by using the extension unit library so as to obtain the shortest path delay. According to the ECO optimization method, on the premise of not remarkably increasing the design cycle, the key path of the multiplier is analyzed, the shortest path delay is realized, and the performance of the multiplier is improved; in addition, the design automation is conveniently implemented, and the ECO optimization method is also suitable for the rear-end ECO optimization of other digital systems.

Description

technical field [0001] The invention relates to the design and optimization of data paths in digital integrated circuits, in particular to an ECO (engineering change order, engineering change order) optimization method for digital multipliers. Background technique [0002] The rapid development of microprocessors is due to the continuous advancement of process technology on the one hand, and the higher and higher performance requirements of the market on the other hand. [0003] The multiplier is an important part in the microprocessor, and its operation speed determines the operating frequency of the logical operation unit, and finally determines the performance of the microprocessor. Therefore, the design and optimization of high-performance multipliers are still concerned. At present, the research on multiplier structure is relatively mature. The mainstream multiplier structure uses the Booth coding algorithm to generate the partial products, and uses the Wallace tree a...

AI Technical Summary

Problems solved by technology

In terms of circuit-level optimization of the multiplier, the traditional method uses larger standard cells in the standard cell library to optimize the multiplier. This method is limited by the limited drive capability of the standard cells in the library and cannot achieve the shortest path. Delay; Another method is to conduct a full custom design for the critical path of the multiplier. This method requires a long design time, delays the product launch process, and it takes up more human resources, and it is not easy to implement the design. automation

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