8 results about "Schottky gate" patented technology

This invention provides a radiation-resistant GaN logic circuit structure and its fabrication method, belonging to the field of semiconductor technology. The circuit structure includes, from bottom to top, a substrate layer, an aluminum nitride nucleation layer, a gallium nitride buffer layer, an aluminum gallium nitride polarization-induced hole transport layer, a gallium nitride channel layer, and a barrier layer. The device has an electrically connected 2DEG resistive region and an enhancement-mode Schottky gate GaN HEMT region. On the surface of the enhancement-mode Schottky gate GaN HEMT region, a drain ohmic electrode, a gate ohmic electrode, a source ohmic electrode, and a HEMT-side deep trench electrode are spaced apart along the source-drain direction. A resistive-side deep trench electrode connected to the gallium nitride buffer layer is disposed on the surface of the 2DEG resistive region, and the resistive-side deep trench electrode and the HEMT-side deep trench electrode are bridged. This effectively prevents hole accumulation at the bottom of the active region, alleviates threshold drift caused by the back-gate effect and fluctuations in the 2DEG resistance, and improves the device's resistance to single-event burn-out.

The invention discloses a longitudinal conduction normally-off type diamond power transistor and a preparation method thereof, and relates to the technical field of semiconductor power devices. The device comprises the following structures: a p-type low-resistance diamond single crystal substrate; the first p-type high-resistance diamond drift layer is located on the upper surface of the p-type low-resistance diamond single crystal substrate; the p-type low-resistance diamond insertion layer is located on the upper surface of the first p-type high-resistance diamond drift layer; the second p-type high-resistance diamond drift layer is located on the upper surface of the p-type low-resistance diamond insertion layer; and the p-type low-resistance diamond cap layer is located on the upper surface of the second p-type high-resistance diamond drift layer. The transistor provided by the invention is provided with the composite epitaxial layer with a multi-layer structure, wherein the on resistance of the diamond power transistor can be reduced and the threshold voltage can be improved by the high-concentration doped low-resistance insertion layer; meanwhile, the low-concentration doped high-resistance drift layer can enable the device to bear higher voltage.

The invention belongs to the technical field of semiconductor device manufacturing, and particularly relates to a preparation method of a P-GaN gate enhanced GaN HEMT (High Electron Mobility Transistor), which comprises the following steps of: sequentially growing a nucleating layer, a cache layer, a channel layer, a barrier layer and a P-type GaN layer on a substrate; forming active region isolation of the device through photoetching and etching processes; photoetching a source electrode region and a drain electrode region, etching to remove the P-type GaN layer in the regions, and depositing and annealing to form N-type ohmic contact; photoetching a P-type ohmic region, reserving a part of the P-type GaN layer on the drain side, etching to remove the rest part, and depositing and annealing to form P-type ohmic contact; photoetching a gate region, and depositing and annealing to form Schottky gate metal; and performing plasma passivation treatment on the P-type GaN between the gate source and the gate drain by taking the gate metal and the P-type ohmic metal as masks, and annealing in a nitrogen atmosphere to convert the P-type GaN into high-resistance GaN. According to the invention, the phenomenon that the device cannot be positively conducted under low drain electrode voltage can be effectively avoided.

The present disclosure provides a semiconductor device and a power device, a 3C-SiC carrier layer is epitaxially grown on a carbon surface (000-1) of a 4H-SiC channel layer, due to the spontaneous polarization of the 4H-SiC channel layer, a 2DEG can be induced at the interface between the 3C-SiC carrier layer and the 4H-SiC channel layer, and a very high 2DEG density can be achieved. Theoretical calculation shows that the 2DEG surface density at the interface can reach 1.28×10 13 / cm 2 Based on this physical property, a power device structure using 2DEG as a control channel is designed, a 2DEG channel region formed based on the heterojunction interface of 3C-SiC and 4H-SiC and a Schottky gate electrode on the surface of 3C-SiC are achieved, and a depletion mode unipolar power device based on electron conduction is achieved. By using the high mobility of the 2DEG formed by the heterojunction interface of 3C-SiC and 4H-SiC, the specific on-resistance of the device is effectively reduced.

The application discloses a GaN-based CMOS device and a preparation method thereof. The GaN-based CMOS device comprises a substrate, a buffer layer, an epitaxial layer and electrodes. The lower surface of the buffer layer is in contact with the substrate. The epitaxial layer is composed of a PMOS region and an NMOS region on the upper surface of the buffer layer. The electrodes comprise an NMOS Schottky gate electrode, an NMOS ohmic electrode arranged in the NMOS region, a PMOS ohmic electrode and a PMOS Schottky gate electrode arranged in the PMOS region. The NMOS Schottky gate electrode and the PMOS Schottky gate electrode are both in a fin structure. The GaN-based CMOS device has a greatly improved carrier mobility, a stronger gate control ability, a smaller gate leakage and a wider practical range.

This invention discloses a method for fabricating high-linearity radio frequency AlGaN / GaN devices: Step 1, selecting AlGaN / GaN and SiC as substrate materials, and depositing a SiN thin film using PECVD; Step 2, exposing interconnect contact holes using photolithography, then etching the SiN and AlGaN barrier layers respectively, and opening the interconnect contact holes in the drift region; Step 3, growing a polycrystalline silicon thin film using LPCVD and performing N-type doping; Step 4, exposing a stacked array structure in the gate-drain region on the interconnect contact holes using photolithography, and... RIE is used to etch the exposed N+Polysi or N+Ge and the underlying SiN to obtain a stacked array pattern along the gate width direction; Step 5, photolithography is performed to expose the source and drain patterns of the ohmic contacts, Ti / Al / Ni / Au is evaporated with an electron beam, and after resist removal and rapid thermal annealing, the source-level ohmic contacts of the device are formed; Step 6, photolithography is performed to expose the Schottky gate pattern, Ni / Au is evaporated with an electron beam to fabricate an RF AlGaN / GaN device with a dual-channel stacked structure of the gate and drain regions.

The invention provides an anti-radiation GaN logic circuit structure and a manufacturing method thereof, and belongs to the technical field of semiconductors. The circuit structure comprises a substrate layer, an aluminum nitride nucleating layer, a gallium nitride buffer layer, an aluminum gallium nitride polarization induced hole transport layer, a gallium nitride channel layer and a barrier layer which are arranged from bottom to top, and the device is provided with a 2DEG resistance region and an enhanced Schottky gate GaN HEMT region which are electrically connected. A drain ohmic electrode, a grid electrode, a source ohmic electrode and an HEMT side deep groove electrode are arranged on the surface of the enhanced Schottky grid GaN HEMT area at intervals in the source-drain direction, a resistor side deep groove electrode connected with the gallium nitride buffer layer is arranged on the surface of the 2DEG resistor area, and the resistor side deep groove electrode is in bridge connection with the HEMT side deep groove electrode. The accumulation of holes at the bottom of the active region can be effectively prevented, the threshold drift and the fluctuation of the 2DEG resistance caused by the back gate effect are relieved, and the single event burnout resistance of the device is improved.

The present invention relates to a gallium nitride (GaN) power transistor (100), comprising: a buffer layer (110); a barrier layer (111) deposited on the buffer layer (110), wherein a gate region (112) is formed on the top of the barrier layer (111); a p-type doped gallium nitride (Gallium Nitride, GaN) A p-type doped GaN layer (113) is deposited on the barrier layer (111) at the gate region (112); and a metal gate layer (114) is deposited on top of the p-type doped GaN layer (113), wherein the metal gate layer (114) contacts the p-type doped GaN layer (113) to form a Schottky barrier (115); wherein the thickness of the p-type doped GaN layer (113), the metal type of the metal gate layer (114), and the p-type doping concentration of the p-type doped GaN layer (113) are based on the known relationship of the pGaN Schottky gate depletion region thickness to the p-type doping concentration and the gate metal type.