4 results about "Schottky gate" patented technology

This invention provides a radiation-resistant GaN logic circuit structure and its fabrication method, belonging to the field of semiconductor technology. The circuit structure includes, from bottom to top, a substrate layer, an aluminum nitride nucleation layer, a gallium nitride buffer layer, an aluminum gallium nitride polarization-induced hole transport layer, a gallium nitride channel layer, and a barrier layer. The device has an electrically connected 2DEG resistive region and an enhancement-mode Schottky gate GaN HEMT region. On the surface of the enhancement-mode Schottky gate GaN HEMT region, a drain ohmic electrode, a gate ohmic electrode, a source ohmic electrode, and a HEMT-side deep trench electrode are spaced apart along the source-drain direction. A resistive-side deep trench electrode connected to the gallium nitride buffer layer is disposed on the surface of the 2DEG resistive region, and the resistive-side deep trench electrode and the HEMT-side deep trench electrode are bridged. This effectively prevents hole accumulation at the bottom of the active region, alleviates threshold drift caused by the back-gate effect and fluctuations in the 2DEG resistance, and improves the device's resistance to single-event burn-out.

The invention discloses a longitudinal conduction normally-off type diamond power transistor and a preparation method thereof, and relates to the technical field of semiconductor power devices. The device comprises the following structures: a p-type low-resistance diamond single crystal substrate; the first p-type high-resistance diamond drift layer is located on the upper surface of the p-type low-resistance diamond single crystal substrate; the p-type low-resistance diamond insertion layer is located on the upper surface of the first p-type high-resistance diamond drift layer; the second p-type high-resistance diamond drift layer is located on the upper surface of the p-type low-resistance diamond insertion layer; and the p-type low-resistance diamond cap layer is located on the upper surface of the second p-type high-resistance diamond drift layer. The transistor provided by the invention is provided with the composite epitaxial layer with a multi-layer structure, wherein the on resistance of the diamond power transistor can be reduced and the threshold voltage can be improved by the high-concentration doped low-resistance insertion layer; meanwhile, the low-concentration doped high-resistance drift layer can enable the device to bear higher voltage.

The invention belongs to the technical field of semiconductor device manufacturing, and particularly relates to a preparation method of a P-GaN gate enhanced GaN HEMT (High Electron Mobility Transistor), which comprises the following steps of: sequentially growing a nucleating layer, a cache layer, a channel layer, a barrier layer and a P-type GaN layer on a substrate; forming active region isolation of the device through photoetching and etching processes; photoetching a source electrode region and a drain electrode region, etching to remove the P-type GaN layer in the regions, and depositing and annealing to form N-type ohmic contact; photoetching a P-type ohmic region, reserving a part of the P-type GaN layer on the drain side, etching to remove the rest part, and depositing and annealing to form P-type ohmic contact; photoetching a gate region, and depositing and annealing to form Schottky gate metal; and performing plasma passivation treatment on the P-type GaN between the gate source and the gate drain by taking the gate metal and the P-type ohmic metal as masks, and annealing in a nitrogen atmosphere to convert the P-type GaN into high-resistance GaN. According to the invention, the phenomenon that the device cannot be positively conducted under low drain electrode voltage can be effectively avoided.

The invention provides an anti-radiation GaN logic circuit structure and a manufacturing method thereof, and belongs to the technical field of semiconductors. The circuit structure comprises a substrate layer, an aluminum nitride nucleating layer, a gallium nitride buffer layer, an aluminum gallium nitride polarization induced hole transport layer, a gallium nitride channel layer and a barrier layer which are arranged from bottom to top, and the device is provided with a 2DEG resistance region and an enhanced Schottky gate GaN HEMT region which are electrically connected. A drain ohmic electrode, a grid electrode, a source ohmic electrode and an HEMT side deep groove electrode are arranged on the surface of the enhanced Schottky grid GaN HEMT area at intervals in the source-drain direction, a resistor side deep groove electrode connected with the gallium nitride buffer layer is arranged on the surface of the 2DEG resistor area, and the resistor side deep groove electrode is in bridge connection with the HEMT side deep groove electrode. The accumulation of holes at the bottom of the active region can be effectively prevented, the threshold drift and the fluctuation of the 2DEG resistance caused by the back gate effect are relieved, and the single event burnout resistance of the device is improved.