Control system and method of low power consumption read-write register

Abstract

The invention discloses a control system of a low power consumption read / write register. The control system comprises a bus interface, a plurality of register modules and a clock generator, wherein, the clock generator comprises clock gate control units that respectively generate clock signals with the frequency lower than that of a bus clock, the clock signals are output to the corresponding register modules to act as a visit clock of the register; the bus interface comprises a read / write data synchronous unit of the register modules which can respectively realize data reading and writing to different register modules of the bus interface. As the invention improves the clock signal generation method involving the read / write part of the register in the control system, leads the working clocks of different register modules to be mutual-independent, and carries out dynamic gate control according to respective work or idle status, and modifies the position of the gate control unit, therefore, the power consumption of the system is greatly reduced.

Description

technical field [0001] The invention relates to a control system and method for reading and writing registers with low power consumption. Background technique [0002] With the continuous development of industrial control technology, the design requirements for low power consumption are becoming more and more stringent, especially in various embedded control systems, low power consumption indicators often become the key to whether new products can be mass-produced and accepted by the market critical factor. [0003] All kinds of control systems involve the read and write operations of registers, and reducing the power consumption of this operation will contribute to the overall low power consumption of the system. figure 1 It is a system structure diagram with a CPU in the prior art. As shown in the figure, all modules related to register reading and writing in the prior art, including the bus interface and each register module, have the same clock signal and are all genera...

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Problems solved by technology

figure 2 It is the circuit diagram of the register module in the prior art, which leads to the situation that the register clock clk_en after the gating is controlled, but the clock clk before the gating unit still exists

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