Method and apparatus for producing wirte-in gating clock signal

Abstract

An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a clock gating signal in response to (i) a write enable signal and (ii) a system clock signal, wherein the clock gating signal is pulsed when the write enable signal operates operate. The second circuit can be configured to generate the above-mentioned write enable signal.

Description

technical field [0001] The invention relates to a clock signal control technology, in particular to a method or circuit for constructing a write-in gating clock signal. Background technique [0002] Existing systems use a free running clock to supply many storage devices. When the enable signal is asserted, new data is acquired at the clock edge. If a continuously operating clock is used as the clock source for the storage device, the storage device still consumes power on every clock edge even if other input data is not moving or unchanged. [0003] Other existing systems use local gated clock units to reduce power consumption. In some systems, when the enable signal is asserted, the clock-gated unit generates a single pulse to capture new data. [0004] refer to figure 1 , where an existing clock network including a clock tree 10 is shown. The clock network includes a clock tree 10, a gated clock unit 12, a flip flop 14, and a number of flip flops 16a-16n. Many clock...

AI Technical Summary

Problems solved by technology

If there are fewer flip-flops than the threshold, which share an enable signal, the flip-flops operate under the clock signal CLK for continuous operation and consume power even if the data does not change

Clock skew balancing for clock nets with gated clock units is more complex and requires more layers of buffers

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