Dual dielectric tri-gate field effect transistor

Abstract

A dual dielectric tri-gate field effect transistor, a method of fabricating a dual dielectric tri-gate field effect transistor, and a method of operating a dual dielectric tri-gate effect transistor are disclosed. In one embodiment, the dual dielectric tri-gate transistor comprises a substrate, an insulating layer on the substrate, and at least one semiconductor fin. A first dielectric having a first dielectric constant extends over sidewalls of the fin, and a metal layer extends over the first dielectric, and a second dielectric having a second dielectric constant is on a top surface of the fin. A gate electrode extends over the fin and the first and second dielectrics. The gate electrode and the first dielectric layer form first and second gates having a threshold voltage Vt1, and the gate electrode and the second dielectric layer form a third gate having a threshold voltage Vt2 different than Vt1.

Description

technical field [0001] The present invention relates generally to semiconductor devices, and more particularly to tri-gate field effect transistors. Background technique [0002] Due to the increasing difficulty in controlling leakage current while shrinking the gate length of complementary metal-oxide-semiconductor (CMOS) transistors, traditional single-gate metal-oxide-semiconductor field-effect transistor (MOSFET) structures can be replaced with double- or triple-gate MOSFET structure instead. These structures allow greater ability to turn off MOSFETs with ultra-short channel lengths by increasing gate control of the channel potential. Among the various multi-gate MOSFET structures developed in recent years, the most promising in terms of manufacturability and performance is the variation of the so-called "FinFET" structure. In these devices, a strip or "fin" of silicon is formed, and the gate material is subsequently deposited and etched such that the resulting gate su...

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Also, since the sidewalls act as gate regions, the potential increase in current available per plane layout

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