SRAM-type FPGA device single-particle inversion detection and error correction circuit
A single-event inversion and circuit technology, applied in the direction of logic circuits using specific components, logic circuits, logic circuits using basic logic circuit components, etc., can solve the problems of increasing chip costs, achieve small chip area and cost, reduce The effect of single event reversal and the realization of anti-SEU function
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[0043] The present invention will be further described below in conjunction with the accompanying drawings, but the embodiments of the present invention are not limited thereto.
[0044] Figure 4 It shows a typical FPGA programming SRAM array (write operation) and its programming verification (read operation) circuit: it is mainly composed of programming control module, address pointer shift register group module, and data shift register group module.
[0045] The programming control module includes an IO interface for external control of chip programming and verification, control state machine (including JTAG TAP control state machine and non-standard serial and parallel programming control state machine), address pointer shift register, Control circuits for data shift registers, boundary scan (Boundary Scan) registers and other shift register groups.
[0046] The address pointer shift register group module includes a shift register and a SRAM word line (Word Line) driver, ...
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