38 results about "Single event latchup" patented technology

The invention discloses a multi-output power supply suitable to be used in a spatial environment, which belongs to the filed of power supply devices. The invention aims to solve the problem that the prior power supply circuit cannot realize the effective protection of a load, nor the detection and protection of a single event latchup event according to the special requirements of the spatial environment. A multipath DC/DC conversion circuit module of the invention has the functions of bus input overcurrent protection and output voltage protection, is connected with a higher-level power supply through a power input filter circuit and connected with a load circuit through n low dropout voltage linear output regulator modules, and outputs an alarming signal to a latch trigger circuit when the current in the load exceeds a preset upper limit of the current so that the latch trigger circuit can control and turn off the n low dropout voltage linear output regulator modules by turning off crow bar circuits and control the n charge-dissipation crow bar circuits to be turned on to release the excessive charges of a load capacitor quickly. The multi-output power supply is used in a spatial environment, and is particularly applicable to the design of modularized joints of a space robot.

The invention discloses a reinforcement method for the single event latchup resistance of a CMOS device. Neutron irradiation is carried out on the CMOS device; a displacement damage is introduced in the neutron irradiation; and a current gain of a parasitical bipolar transistor in an inverter of the CMOS device is reduced, so that P-N-P-N latchup is not generated. The reinforcement method is an external reinforcement method; processing steps to produce the device will not be increased; there is no need to redesign a device layout for the single event latchup effect; and complexity of an original system will not be increased. Thus, the fixed size of the device will not be changed, and a peripheral circuit will not be increased either.

The invention belongs to the technical field of space radiation effect and strengthening, and particularly relates to an on-track monitoring method for space single event latchup effect. The method is based on a precision resistor, an over-current detection circuit, a counting latch, a latchup protection switching circuit, a power system and a watch dog counting circuit, wherein the watch dog counting circuit comprises two stages; the precision resistor is connected with the over-current detection circuit; the over-current detection circuit is also connected with the counting latch and the latchup protection switching circuit; the latchup protection switching circuit is also connected with the watch dog counting circuit and the power system. The monitoring method can realize space single event latchup effect monitoring of different track environment, and simultaneously provides a quick and accurate universality method for monitoring and evaluating deep space detection single event latchup effect.

A delay flip-flop comprises a clock module, a delay filtering module, a master-slave DICE latch module and an output module, wherein the master-slave DICE latch module outputs a corresponding data signal to the data output module according to a clock signal that is output from the clock module and an outer data signal that is received through the delay filtering module. The master-slave DICE latch module is composed of a master-grade module and a slave-grade module. The delay filtering module is used for preventing entering of a transient pulse which is caused by a single event effect into the register. The master-slave DICE latch module is used for correcting inner node upset which is caused by the single-particle effect. The delay filtering module performs a function of preventing a single event transient pulse. The master-slave DICE latch module prevents overturning of an inner storage node, thereby performing a function of preventing single event upset. A protective belt structure is added in layout design. The structure of the delay flip-flop effectively restrains single event latchup, and facilitates reduction of a single event transient pulse width in a circuit.

A method for testing an integrated circuit for potential latchup sites includes applying a voltage to the integrated circuit, measuring a current through the integrated circuit, applying at least one radiation beam to at least one area of the integrated circuit, and detecting an occurrence of a latchup by detecting an increase of the current through the integrated circuit upon applying the at least one radiation beam to the at least one area of the integrated circuit.

Method for SEL mitigation involves determining one or more base sets of signature vector components for each of a plurality of signal loading conditions experienced by a protected device in an operating state, each set of base signature vector components together comprising a base signature vector. The method further involves monitoring signature vector components for the protected device to determine a detected signature vector which is comprised of a set of detected signature vector components. The detected signature vector is compared to a dynamically selected base signature vector which is associated with the device state and signal loading condition which are currently active to differentiate between the occurrence of standard current surges associated with normal operation of the protected device and a non-standard current surge.

A delay flip-flop with a reset terminal comprises a clock module, a delay filtering module, a master-slave DICE latch module and an output module, wherein the master-slave DICE latch module outputs a corresponding data signal to the data output module according to a clock signal that is output from the clock module and an outer data signal that is received through the delay filtering module. The master-slave DICE latch module is provided with the reset terminal. The delay filtering module is used for preventing entering of a transient pulse which is caused by a single event effect into the register. The master-slave DICE latch module is used for correcting inner node upset which is caused by the single-particle effect. The reset terminal is used for resetting the output end. The delay filtering module performs a function of preventing a single event transient pulse. The master-slave DICE latch module prevents overturning of an inner storage node, thereby performing a function of preventing single event upset. A protective belt structure is added in layout design. The structure of the delay flip-flop effectively restrains single event latchup, and facilitates reduction of a single event transient pulse width in a circuit.

An electronic circuit for single-event latch-up (SEL) detection and protection of a target integrated circuit (IC) is disclosed. The circuit comprises: a first detector configured for detecting an absolute load current (i) and comparing the absolute load current (i) with a threshold current (i_th); a second detector configured for detecting a rate of change of load current (di/dt) and comparing the rate of change of load current (di/dt) with a threshold current change rate (di/dt)_th; and a determination module for triggering a power shut-down to the target IC if the absolute load current (i) exceeds the threshold current (i_th) and/or the rate of change of load current (di/dt) exceeds the threshold current change rate (di/dt)_th.

The invention relates to a D flip-flop with a set terminal. The D flip-flop comprises a clock module, a delay filtering module, a master-slave DICE latch module and an output module, wherein the master-slave DICE latch module is used for outputting corresponding data signals to a data output module according to clock signals output from the clock module and external data signals received through the delay filtering module. The master-slave DICE latch module is provided with the set terminal; the delay filtering module is used for preventing transient pulses caused by a single event effect from entering inside a register; the master-slave DICE latch module is used for correcting internal node upsetting caused by the single event effect; the set terminal is used for setting an output terminal to be 1; the delay filtering module plays a role in resisting SET (Single Event Transient), the master-slave DICE latch module is used for preventing internal storage nodes from upsetting and plays a role in resisting SEU (Single Event Upset), and a guard band structure is added during layout designing, is used for effectively inhibiting SEL (Single Event Latchup) and is also beneficial to the reduction of SET pulse width in a circuit.

Provided is an integrated circuit. The integrated circuit includes an array of random-access memory cells is provided. Each memory cell may include inverting circuits formed from pull-up transistors and pull-down transistors and also access transistors coupled to the inverting circuits. The pull-up transistors may be formed in an n-well. The memory cells may also be coupled to single event latch-up (SEL) prevention circuitry. The SEL prevention circuitry may include a clamping circuit, a voltage sensing circuit, and a driver circuit. In response to a single event alpha particle strike at one of the memory cells, a temporary voltage rise may be presented at the clamping circuit. The voltage sensing circuit may detect the voltage rise and direct the driver circuit to bias the n-well into deep reverse bias region. Operated in this way, the SEL prevention circuitry can mitigate SEL while minimizing memory cell leakage.

An apparatus that includes a single event latchup (SEL) recovery circuit, a microprocessor operatively connected with the SEL recovery circuit, and an output maintenance circuit that maintains a state of the microprocessor prior to a power cycle of the microprocessor. The apparatus is configured to detect a SEL event or other fault via a watchdog circuit, initiate a power cycle of the microprocessor, retain a latch state from the microprocessor, and determine whether the microprocessor was restarted due to an SEL event. Responsive to determining that the microprocessor has failed to restart due to a persistent fault, the apparatus determines whether a prepower cycle limit is reached within a predetermined span of time, and selectively provide power to a load based on the latch state and the power cycle limit determination.

A radiation-hardened transistor is formed in a p-type body. An active region is disposed within the p-type body and has a perimeter defined by a shallow-trench isolation region filled with a dielectric material. Spaced-apart source and drain regions are disposed in the active region, forming a channel therebetween. A polysilicon gate is disposed above, aligned with, and insulated from the channel region. A p-type isolation ring is disposed in the p-type body separating outer edges of at least one of the source and drain regions from the perimeter of the active region. A body contact is disposed in the p-type isolation ring.

The invention discloses a circuit module capable of preventing surge and single event latchup for on-satellite equipment. The circuit module comprises a power switch K1, a diode D1, resistors R1, R2,R3, R4, R5, R6 and R7, triodes Q1 and Q2, capacitors C1 and C2 and a power field effect transistor Q3. The circuit module integrates an anti-surge circuit and a single event latchup preventing circuitto enable the circuit module to have an anti-surge function and a single event latchup prevention function simultaneously, thereby effectively reducing voltage drop of the power end, improving equipment efficiency, reducing equipment power consumption and improving global stability of the system.