Delay flip-flop with reset terminal

A technology of clearing the terminal and trigger, applied in the direction of pulse generation, electrical components, generating electrical pulses, etc., can solve problems such as affecting subsequent operations, adverse system work, system errors or crashes

Active Publication Date: 2015-08-05
NO 47 INST OF CHINA ELECTRONICS TECH GRP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

D flip-flop is the most widely used sequential device in integrated circuits. After single-event flipping and single-event transient, this kind of device will retain the error information and affect the subsequent operation, w

Method used

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  • Delay flip-flop with reset terminal
  • Delay flip-flop with reset terminal
  • Delay flip-flop with reset terminal

Examples

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Embodiment Construction

[0030] Below in conjunction with accompanying drawing, invention is described in further detail.

[0031] Such as figure 1 As shown, a D flip-flop with a reset terminal according to an embodiment of the present invention includes a clock module 1 , a delay filter module 2 , a master-slave DICE latch module 3 , and an output module 4 . The master-slave DICE latch module includes a master module 31 and a slave module 32 . Both the master and slave stages are reinforced with DICE, and a delay filter module 2 is added to the data end.

[0032] The clock signal output of the clock module 1 is connected to the clock signal input of the master-slave DICE latch module 3, the data input of the delay filter module 2 is connected to the data source, and the data output is connected to the master-slave DICE latch The data input end of the module 3 is connected, and the data output end of the master-slave DICE latch module 3 is connected to the signal input end of the output module 4 . ...

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PUM

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Abstract

A delay flip-flop with a reset terminal comprises a clock module, a delay filtering module, a master-slave DICE latch module and an output module, wherein the master-slave DICE latch module outputs a corresponding data signal to the data output module according to a clock signal that is output from the clock module and an outer data signal that is received through the delay filtering module. The master-slave DICE latch module is provided with the reset terminal. The delay filtering module is used for preventing entering of a transient pulse which is caused by a single event effect into the register. The master-slave DICE latch module is used for correcting inner node upset which is caused by the single-particle effect. The reset terminal is used for resetting the output end. The delay filtering module performs a function of preventing a single event transient pulse. The master-slave DICE latch module prevents overturning of an inner storage node, thereby performing a function of preventing single event upset. A protective belt structure is added in layout design. The structure of the delay flip-flop effectively restrains single event latchup, and facilitates reduction of a single event transient pulse width in a circuit.

Description

technical field [0001] The invention relates to the field of semiconductor devices, in particular to a D flip-flop with a reset terminal. Background technique [0002] When a semiconductor device is in a radiation environment, the surrounding energy particles will penetrate into the chip and generate ionizing radiation, which will generate a certain number of electron and hole pairs on the trajectory of the energy particles. These electrons and holes generated by the ionizing radiation of single energy particles may be absorbed by the internal nodes of the circuit under the action of the electric field, resulting in abnormal function of the semiconductor device. These effects are called single event effects. [0003] A single event effect is a random effect. In 1975, people discovered the abnormal flip phenomenon of Binder, communication satellites, and JK triggers. After continuous research, it was found that the factors that caused the abnormal flip phenomenon included h...

Claims

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Application Information

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IPC IPC(8): H03K3/3562
Inventor 陈智王爽
Owner NO 47 INST OF CHINA ELECTRONICS TECH GRP
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