A kind of d flip-flop with clear terminal
A technology for clearing terminals and flip-flops, which is applied in the direction of pulse generation, electrical components, and electric pulse generation, and can solve problems such as system errors or crashes, unstable D flip-flops, and unfavorable system work.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Publication Date
- 2017-07-07
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Abstract
Description
technical field
[0001] The invention relates to the field of semiconductor devices, in particular to a D flip-flop with a reset terminal. Background technique
[0002] When a semiconductor device is in a radiation environment, the surrounding energy particles will penetrate into the chip and generate ionizing radiation, which will generate a certain number of electron and hole pairs on the trajectory of the energy particles. These electrons and holes generated by the ionizing radiation of single energy particles may be absorbed by the internal nodes of the circuit under the action of the electric field, resulting in abnormal function of the semiconductor device. These effects are called single event effects.
[0003] A single event effect is a random effect. In 1975, people discovered the abnormal flip phenomenon of Binder, communication satellites, and JK triggers. After continuous research, it was found that the factors that caused the abnormal flip phenomenon included h...
Examples
Embodiment Construction
[0030] Below in conjunction with accompanying drawing, invention is described in further detail.
[0031] like figure 1 As shown, a D flip-flop with a reset terminal according to an embodiment of the present invention includes a clock module 1 , a delay filter module 2 , a master-slave DICE latch module 3 , and an output module 4 . The master-slave DICE latch module includes a master module 31 and a slave module 32 . Both the master and slave stages are reinforced with DICE, and a delay filter module 2 is added to the data end.
[0032] The clock signal output of the clock module 1 is connected to the clock signal input of the master-slave DICE latch module 3, the data input of the delay filter module 2 is connected to the data source, and the data output is connected to the master-slave DICE latch The data input end of the module 3 is connected, and the data output end of the master-slave DICE latch module 3 is connected to the signal input end of the output module 4 .
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