Single-event upset immune frequency divider circuit

Abstract

A single-event upset immune frequency divider circuit is disclosed. The single-event upset immune frequency divider circuit includes a dual-path shift register, a dual-path multiplexor, and a summing circuit. The dual-path shift register has a clock input, one signal input pair and multiple signal output pairs. The dual-path multiplexor has multiple signal input pairs and one output pair. The signal input pairs of the dual-path multiplexor are respectively connected to the signal output pairs of the dual-input shift register. The dual-path multiplexor selects one of the signal output pairs of the dual-path shift register for feeding back into the signal input pair of the dual-path shift register. The summing circuit then sums the signal input pair of the dual-path shift register to generate an output clock signal that is a fraction of the frequency of an input clock signal at the clock input of the dual-path shift register.

Description

RELATED PATENT APPLICATION[0001] The present patent application is related to a copending application U.S. Ser. No. 09 / ___,___ filed on even date, entitled "SINGLE-EVENT UPSET IMMUNE FLIP-FLOP CIRCUIT" (Attorney Docket No. BA-00578).[0002] 1. Technical Field[0003] The present invention relates to electronic circuits in general, and in particular to frequency divider circuits. Still more particularly, the present invention relates to a single-event upset immune frequency divider circuit.[0004] 2. Description of the Related Art[0005] Frequency divider circuits are commonly used in electronic devices that include counting circuits, phase-locked loop circuits, and / or frequency synthesizer circuits. Generally speaking, frequency dividers are used to generate signals of relatively lower frequencies by dividing a high frequency signal already existed within an electronic system. For example, if a 50 MHz signal is desired from a 100 MHz clock signal existed within an electronic system, a fr...

AI Technical Summary

Benefits of technology

The present invention provides a single-event upset (SEU) immune frequency divider circuit that is designed to be resistant to single-event upsets (SEUs) that can occur in electronic circuits. The circuit includes a summing circuit, a dual-path shift register, and a dual-path multiplexor. The circuit is designed to selectively feed back one of the output pairs of the dual-path shift register to the input pair of the dual-path shift register, allowing for a more robust and reliable output clock signal. The technical effect of this invention is to provide a more reliable and robust frequency divider circuit that is resistant to SEUs.

Problems solved by technology

One problem with prior art frequency divider circuits, such as frequency divider circuit 10, is that they are very susceptible to single-event upsets (SEUs) or single-event transients (SETs) that can result in runt pulses occurred on the clock path and subsequently phase shifts in the output signals.

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