28 results about "Interconnect architecture" patented technology

An interconnect fabric may comprise a plurality of interconnect routing devices (IRDs) coupled in a mesh topology via general-purpose wires that are configurable to carry different combinations of message types, and each message type may belong to a different logical channel. Each IRD may be operable to receive concurrently, from a set of input interfaces, multiple messages belonging to one or more message types. Each IRD may be operable to map the multiple messages to one or more output interfaces from a set of output interfaces based on a destination of each message. Each IRD may be further operable to send, for each of the mapped output interfaces, the messages mapped to the output interface as a combination of logical channels onto a set of general-purpose wires of the output interface, wherein each of the general-purpose wires is operable to dynamically switch between carrying messages of different message types.

In one embodiment, an A / V interconnection architecture is provided that includes a TX A / V endpoint that supports native audio and stereo down-mixed audio on separate networks. The TX A / V endpoint outputs native audio over a video network to an RX A / V endpoint coupled to an A / V sink component that is capable of processing or outputting the native audio, and produces a stereo down-mixed version of the native audio which is output over an audio network to an audio system coupled to an audio sink component that is incapable of handling the native audio. In another embodiment, an A / V interconnection architecture is provide that enables expandable surround sound. If the number of audio channels for a type of surround sound is less than or equal to a number of local amplified output channels, surround sound is provided using only local unpowered speakers. If the number exceeds the number of the local amplified output channels, surround sound is provided using both the local unpowered speakers and one or more add on devices accessible over the audio network.

A wafer-scale compute system integrates multiple semiconductor stacks on a monolithic passive silicon substrate patterned into mechanically isolated silicon islands interconnected through through-silicon vias and redistribution wiring layers. Etched silicon spring structures provide in-plane and out-of-plane compliance, enabling wafer-scale assembly without mechanical stress. The substrate includes redundant wiring and multiple regulated power domains supplied by vertical modules. All communication between stacks occurs through the silicon substrate, forming a contiguous all-silicon computational domain with no organic circuit boards or interposers. The architecture delivers zetta-scale performance with high yield and mechanical reliability.

The invention relates to an electrical structure comprising: (a) functional modules, which are both capable of acting as transaction initiators and as transaction targets, so that a transaction initiator functional module can require a transaction target functional module to perform functions for and on its behalf; (b) a first interconnect architecture connecting the functional modules and providing communication between them; wherein the (electrical) structure is arranged such that a selected transaction initiator functional module is capable of temporarily exclusively accessing the transaction target functional module(s) performing functions for and on its behalf to ensure that transaction initiator functional modules other than the selected transaction initiator functional module cannot access it uncontrolled, wherein said selected transaction initiator functional module is a hardware security module.

The disclosure provides an evaluation device of a FPGA interconnection architecture based on a graph neural network, which comprises: an input unit configured to obtain description information of a target FPGA architecture and corresponding timing report information; an intra-block graph construction unit configured to obtain corresponding wiring resource graphs and global features according to the description information conversion; a node frequency label extraction unit configured to obtain frequency information of critical path node occurrence according to the timing report information; and a prediction unit configured to obtain the routability and area delay product value of the target FPGA according to the obtained wiring resource graphs and global features and the frequency information of critical path node occurrence. The evaluation device provided in some embodiments of the disclosure can predict the routability and area delay product of the interconnection architecture through the GEF model, and significantly reduce the number of calls of the traditional evaluation tool.

Electrical interconnection architectures for electrically connecting stacked prismatic battery modules in various combinations of parallel and series configurations distribute heat sources (e.g., heat conduction through a busbar and internal resistance heating from short-circuiting) to multiple battery cells rather than a single adjacent cell, thereby reducing the propagation of thermal displacement. Examples of interconnection architectures include various combinations of overlap bus and bypass bus configurations. A two-parallel module configuration can have two series submodules with cells connected in a staggered interconnection pattern. A busbar interconnection pattern can allow the negative inlet and positive outlet to be located at the same end of a battery module. Battery cells can be interconnected such that a parallel cell is not an adjacent cell.Various combinations of resistors and fuses can also be used to reduce overheating caused by short circuits.

Selective data compression for non-critical memory requests is described. In accordance with the described techniques, memory request packets are generated and communicated for retrieval of data from computer memory, and data packets including the retrieved data are communicated to a hardware compression engine. The compression engine selectively compresses the retrieved data and the compressed data is communicated through an interconnect architecture for decompression by a decompression engine. The compression of the data decreases communication congestion within the interconnect architecture. The memory request packets are configurable to include metadata providing hints to the compression engine to guide selective compression of data.

Systems and methods for an interconnect architecture for Out-of-Band (OOB) manageability in heterogeneous computing platforms. In some embodiments, an Information Handling System (IHS) may include a heterogeneous computing platform having a plurality of devices and an OOB Microcontroller Unit (MCU) integrated into the heterogeneous computing platform, where the OOB MCU is configured to: receive a command; and transmit the command or an indication of the command to a selected one of the plurality of devices via an interconnect while a host processor is in a low-power state.

The invention relates to a hardware architecture simulation tool oriented to system-level chip interconnection optimization, which is characterized in that a processor core, a cache controller, a memory controller and an on-chip interconnection network model with an accurate period are integrated in a full-system joint simulation framework, and the conversion between a cache consistency message and an interconnection data unit is realized through a network interface controller; network delay is fed back to a system simulation scheduler with cycle-level precision, an interconnection network adopts a router micro-architecture with an accurate cycle for modeling, key stages such as buffering, routing, virtual channel distribution, switch distribution and link traversal are finely depicted, and virtual channel flow control and a point-to-point sorting mechanism are combined, so that the routing efficiency is improved. And a power consumption analysis model based on activity counting is introduced, and the dynamic power consumption and the static leakage power consumption of the interconnection network are accurately evaluated. According to the application, various network topologies, routing strategies and hardware parameter configurations are supported, and the comprehensive influence of the interconnection architecture on the performance and energy efficiency of the chip is accurately evaluated at the system level.

A scalable multiband wavelength division multiplexing (WDM) transceiver architecture suitable for high bandwidth optical computing interconnect (OCI) between computing resources. The WDM wavelength range is divided into two or more color / wavelength bands. Each band of the WDM optical signal may be coupled by separate semiconductor optical amplifiers (SOAs) that are tuned to different bands. The wavebands may be transmitted over an optical MUX / DeMUX for transmission over an optical fiber. The optical MUX / DeMUX may include a band MUX / DeMUX or a polarization MUX / DeMUX.

In one embodiment, an apparatus includes a first integrated circuit die with metal bonding pads that are co-planar with an external surface of the die and a second integrated circuit die with metal bonding pads that are co-planar with an external surface of the die. The first and second integrated circuit dies are coupled together such that their external surfaces are in contact and the metal pads of the first integrated circuit die are in direct contact with respective metal pads of the second integrated circuit die. The apparatus also includes an inductor formed at least partially by the metal pads of the first integrated circuit die and the metal pads of the second integrated circuit die.

Methods and apparatuses are provided that can establish data links with greater bandwidths within die-to-die interconnect architectures. In one example, a system-on-a-chip (SoC) includes an error status register, a plurality of data ports for a data link, and a processor electrically coupled to the error status register and to the plurality of data ports. The processor can receive error data from the error status register and, based on the error data, can determine a portion of the plurality of data ports that are error free. Further, the processor can determine a bandwidth for the data link based on the portion of the plurality of data ports that are error free. Further, the processor can initiate a link negotiation process to establish the link with another device based on the link width value and the portion of the plurality of data ports that are error free.

Methods and apparatuses are provided to detect errors within device link sessions, and to disable the link sessions based on the detected errors. In one example, a die includes a non-transitory, machine-readable storage medium storing instructions. The die also includes at least one processor coupled to the non-transitory, machine-readable storage medium. The at least one processor is configured to execute the instructions to detect an error within a link session with a device. The at least one processor is also configured to execute the instructions to decrement an index value corresponding to the link session based on the detected error. Further, the at least one processor is configured to execute the instructions to compare the index value to a threshold value. The at least one processor is also configured to execute the instructions to disable the link session with the device based on the comparison.

The invention discloses an optical interconnection architecture, the optical interconnection architecture comprises an XPU board card, the XPU board card comprises a semiconductor chip and an optical I / O module, the optical I / O module comprises an optical driver, an optical detector array and a two-dimensional array light source, and the optical driver is electrically connected to one side of the semiconductor chip through a micro bump or direct bonding technology. The optical interconnection architecture provided by the invention has the advantages of low system complexity, short signal transmission path, low time delay and low energy consumption.

The invention discloses a system-on-chip interconnection architecture conflict optimization method based on pin multiplexing constraint. The method comprises the following steps: in a system-on-chip interconnection architecture, receiving a host access request and determining a target exchange switch group and a target slave; judging whether the target slave machine belongs to a multiplexing sensing type exchange switch group which is fixedly connected with peripheral equipment with a pin multiplexing relation in a design stage or not; if yes, querying a pin multiplexing controller to obtain a current activated peripheral identifier of the corresponding physical pin group; and based on the comparison result of the target slave identification and the currently activated peripheral identification and the busy / idle state of the exchange switch group, conflict awareness arbitration is executed, and the decision processing mode comprises immediate execution, execution permission, immediate rejection or suspension waiting. According to the method, the physical pin multiplexing constraint is fused into interconnection network hardware design and runtime arbitration, invalid access is actively prevented from the hardware level, the system resource utilization rate is improved, the software complexity is reduced, and the response certainty is enhanced.

Electrical interconnection architectures for electrically connecting stacked prismatic battery modules in various combinations of parallel and series configurations that distribute heat sources (e.g., heat conduction through a busbar, and internal resistance heating from short circuiting) to multiple battery cells, rather than to a single adjacent cell, thereby reducing thermal excursion propagation. Examples of interconnection architectures include various combinations of overlap bus and bypass bus configurations. A two-parallel module configuration may have two serial sub-modules with cells connected in a staggered interconnection pattern. A busbar connection pattern may allow the negative inlet and positive outlet to be located on the same end of a battery module. Battery cells may be interconnected so that a parallel cell is not an adjacent cell. Various combinations of resistors and fuses may also be used to reduce overheating from short circuiting.

The application discloses a 3D FPGA interconnection architecture based on a configurable repeater, which comprises a plurality of layers of dies; the vertical direction of the die comprises a post-wiring, a configurable repeater unit and a through silicon via in a silicon substrate region in sequence; the configurable repeater unit comprises an input selector, a mode selection and signal path, an output driver and a configuration memory, wherein the mode selection and signal path comprises three modes, which are a pass-through mode, a latching mode and a terminal mode. The application constructs a special low-delay data channel through a plurality of chips through the CRU pass-through mode, supports dynamic reconfiguration to adapt to traffic changes while significantly reducing transmission delay and area overhead, and can effectively absorb the reflection energy of unused branches to guarantee signal integrity, thereby providing a high-energy-efficiency and high-reliability interconnection solution for large-scale streaming data transmission.

The systems and methods of the present invention are used to efficiently and effectively incorporate processing power into internal memory. In one embodiment, a processing-in-memory (PIM) chip includes a memory array, logic components, and an interconnect network. The memory array is used to store information. In an exemplary implementation, the memory array includes memory cells and array peripheral components. The logic components are capable of processing the information stored in the memory array. The interconnect network is used to communicatively couple the logic components. The interconnect network may include interconnects, and a portion of the interconnects may be located in a metal layer region that is located above the memory array.

The semiconductor module includes two or more semiconductor dies and an interconnect structure coupled to the two or more semiconductor dies, the interconnect structure implementing a plurality of inter-die connection paths having a first density and a plurality of fan-out rewiring paths having a second density different from the first density.

Methods and apparatuses are provided that can establish data links with greater bandwidths within die-to-die interconnect architectures. In one example, a system-on-a-chip (SoC) includes an error status register, a plurality of data ports for a data link, and a processor electrically coupled to the error status register and to the plurality of data ports. The processor can receive error data from the error status register and, based on the error data, can determine a portion of the plurality of data ports that are error free. Further, the processor can determine a bandwidth for the data link based on the portion of the plurality of data ports that are error free. Further, the processor can initiate a link negotiation process to establish the link with another device based on the link width value and the portion of the plurality of data ports that are error free.

The present disclosure relates to non-reliable, out-of-order data transfers over a memory interconnect architecture. An inter-process communication method divides a total payload of a first memory command among a plurality of packets and encodes a last transmitted packet of the plurality of packets to include a metadata code in the total payload. The memory command can be transmitted between processes that perform a collective operation. Payloads of the packets are written to memory in a sequential address order such that the metadata code is written to a particular address and a second process generates an acknowledgement to the first memory command to the first process on a condition that the metadata code is read back from the particular address.

The invention relates to a verification method for AMBA bus matrix interconnection based on a UVM, provides a complete verification system for AMBA bus matrix interconnection, and comprises three stages: 1, constructing a verification platform, 2, constructing a test case, and 3, designing a test process. On the basis of a UVM verification methodology, a verification platform for AMBA bus matrix interconnection is built by using a VIP component of an AMBA bus. And sending a test case to the interfaces at the two ends of the master device and the slave device of the to-be-verified bus matrix interconnection architecture through the verification platform for verification. Feedback output of the bus matrix is obtained from the bus matrix interface, the verification platform collects, compares and analyzes feedback output results, and a test result is reported.

Embodiments herein relate to an interconnect architecture for a multi-transistor stack including channel structures in the form of nanoribbons or nanowires. In one aspect, a metal interconnect is routed between the transistors to provide between electrical connections for control gates and / or source / drain nodes of the transistors. The electrical connections can be provided between transistors in the same stack or in different stacks. In another aspect, control gates of transistors in a stack are independently controlled.

The invention belongs to the technical field of integrated circuit design and communication interfaces, and particularly relates to an interconnection architecture and an interconnection method of SerDes and PCS. The interconnection architecture comprises a SerDes, a PCS and a SerDesBus located between the SerDes and the PCS. The SerDesBus comprises dispatchers and a bus; the dispatchers are respectively positioned on the left side and the right side of the SerDesBus; the bus is used for transmitting data to opposite directions; the scheduler is used for scheduling the SerDes Lane and distributing a basic unit Sat for the SerDes Lane, wherein the basic unit Sat is used for transmitting data on the SerDes Bus; and each SerDes Lane and each PCS Lane are respectively connected with the two slave buses through different transmitting lines and different receiving lines. The SerDes Bus which is composed of two buses and comprises two dispatchers is adopted for data transmission, and interconnection between any SerDes Lane and any PCS Lane can be achieved.

Methods and apparatuses are provided that can establish data links with greater bandwidths within die-to-die interconnect architectures. In one example, a system-on-a-chip (SoC) includes an error status register, a plurality of data ports for a data link, and a processor electrically coupled to the error status register and to the plurality of data ports. The processor can receive error data from the error status register and, based on the error data, can determine a portion of the plurality of data ports that are error free. Further, the processor can determine a bandwidth for the data link based on the portion of the plurality of data ports that are error free. Further, the processor can initiate a link negotiation process to establish the link with another device based on the link width value and the portion of the plurality of data ports that are error free.

The invention belongs to the technical field of simulation acceleration. The invention provides an inter-processor interconnection architecture for a hardware simulation acceleration system. According to the layered interconnection network architecture provided by the embodiment of the invention, a large-size crossbar switch is decomposed into a combination of a plurality of small-size multiplexer arrays, and the combination is divided into an intra-cluster network, a Boolean processor inter-cluster network and a TDM interface cluster interconnection network for connection, so that the chip area and the wiring complexity are remarkably reduced. Meanwhile, the performance evaluation method of the interconnection architecture between the processors is matched, and high-precision and high-efficiency simulation can be carried out on the interconnection architecture. The performance of different interconnection structures in the aspects of communication cycle number, area, utilization rate and the like can be accurately evaluated, and a key basis is provided for interconnection network optimization. Interconnection resource consumption and communication delay of the simulation acceleration chip are effectively reduced, a regular topological structure of the simulation acceleration chip facilitates task scheduling and optimization of a compiler, and the overall simulation efficiency and debuggeability are improved.

The present disclosure provides a method and apparatus for realizing mutual access of storage spaces in a GPU interconnect architecture, a computing device, a computer program product, and a computer readable storage medium. The GPU interconnect architecture comprises a plurality of interconnected GPU boards; each GPU board comprises a processing apparatus, a storage apparatus, a routing apparatus, and a plurality of ports adapted to be communicated with other GPU boards; the storage apparatus of each GPU board has a respective local address range; the plurality of local address ranges are uniformly addressed to form a global address. The method comprises: a routing apparatus of a first GPU board receives an access request and parses same to obtain an address segment, to be accessed by the access request, in a global address; the routing apparatus of the first GPU board determines a GPU board corresponding to the address segment, to be accessed by the access request, in the global address; and the routing apparatus of the first GPU board maps the access request to a storage apparatus of the corresponding GPU board.

Methods and apparatus are provided for reducing latency associated with state transitions in a die-to-die interconnect architecture. In one example, a physical layer of a die detects a first event indicating a transition to a lower power state. In response to a first event, the physical layer transitions to a lower power state in which one or more clock configuration values are read from the register and stored in the memory. The physical layer then detects a second event indicating a transition to an active state. In response to a second event, the physical layer reads the clock configuration value from the memory and writes the clock configuration value to the register. The physical layer then transitions to a power stable state and remains in the power stable state for an amount of time to allow clock stabilization. The physical layer then transitions to a training state.