36 results about "Interconnect architecture" patented technology

The invention relates to the technical field of direct current motor servo drive control, and provides a Zynq AXI4 bus-based real-time transmission system and a control method thereof, and the system comprises a Zynq system on chip, a DDR3 common data area, an AXI4 bus interconnection architecture and a dynamic partition manager. By implementing the scheme, firstly, the multi-channel characteristic of the AXI4 bus is utilized, special transmission channels are distributed for different types of data, and parallel data interaction is realized; secondly, a dynamic partition manager is deployed at a PL end, a DDR3 public data area is dynamically divided into a plurality of partitions in real time according to needs, multi-task parallel is achieved, and the real-time performance of the system is improved; thirdly, the read-write operation on the DDR3 in each control period is split into a plurality of state machines through precise scheduling of the state machines, the state machines are combined into a state loop to be mounted to an AXI4 bus, it is ensured that key tasks are completed on time, and the certainty of the system is improved; fourthly, the size and the number of partitions in the DDR3 are dynamically adjusted through a dynamic partition manager, and the storage efficiency is improved.

The application discloses a chip based on a reconfigurable neuromorphic interconnection architecture, comprising a layered dynamic reconfigurable interconnection network layer and a memristor-CMOS reconfigurable interconnection unit, and the layered dynamic reconfigurable interconnection network layer and the memristor-CMOS reconfigurable interconnection unit are dynamically adjusted in a routing path through a dynamic routing algorithm. The application has the beneficial effects that: the dynamic routing algorithm is combined with the layered dynamic reconfigurable interconnection network layer and the memristor-CMOS reconfigurable interconnection unit, thereby performing dynamic prediction of network congestion and dynamic adjustment of a routing path, and the CMOS switch and the memristor switch are connected in parallel, avoiding the limitation of traditional single devices or static interconnections, so that the network performance and reliability are improved, and the delay and power consumption of data transmission are reduced.

An interconnect fabric may comprise a plurality of interconnect routing devices (IRDs) coupled in a mesh topology via general-purpose wires that are configurable to carry different combinations of message types, and each message type may belong to a different logical channel. Each IRD may be operable to receive concurrently, from a set of input interfaces, multiple messages belonging to one or more message types. Each IRD may be operable to map the multiple messages to one or more output interfaces from a set of output interfaces based on a destination of each message. Each IRD may be further operable to send, for each of the mapped output interfaces, the messages mapped to the output interface as a combination of logical channels onto a set of general-purpose wires of the output interface, wherein each of the general-purpose wires is operable to dynamically switch between carrying messages of different message types.

In one embodiment, an A / V interconnection architecture is provided that includes a TX A / V endpoint that supports native audio and stereo down-mixed audio on separate networks. The TX A / V endpoint outputs native audio over a video network to an RX A / V endpoint coupled to an A / V sink component that is capable of processing or outputting the native audio, and produces a stereo down-mixed version of the native audio which is output over an audio network to an audio system coupled to an audio sink component that is incapable of handling the native audio. In another embodiment, an A / V interconnection architecture is provide that enables expandable surround sound. If the number of audio channels for a type of surround sound is less than or equal to a number of local amplified output channels, surround sound is provided using only local unpowered speakers. If the number exceeds the number of the local amplified output channels, surround sound is provided using both the local unpowered speakers and one or more add on devices accessible over the audio network.

A wafer-scale compute system integrates multiple semiconductor stacks on a monolithic passive silicon substrate patterned into mechanically isolated silicon islands interconnected through through-silicon vias and redistribution wiring layers. Etched silicon spring structures provide in-plane and out-of-plane compliance, enabling wafer-scale assembly without mechanical stress. The substrate includes redundant wiring and multiple regulated power domains supplied by vertical modules. All communication between stacks occurs through the silicon substrate, forming a contiguous all-silicon computational domain with no organic circuit boards or interposers. The architecture delivers zetta-scale performance with high yield and mechanical reliability.

The invention relates to an electrical structure comprising: (a) functional modules, which are both capable of acting as transaction initiators and as transaction targets, so that a transaction initiator functional module can require a transaction target functional module to perform functions for and on its behalf; (b) a first interconnect architecture connecting the functional modules and providing communication between them; wherein the (electrical) structure is arranged such that a selected transaction initiator functional module is capable of temporarily exclusively accessing the transaction target functional module(s) performing functions for and on its behalf to ensure that transaction initiator functional modules other than the selected transaction initiator functional module cannot access it uncontrolled, wherein said selected transaction initiator functional module is a hardware security module.

The disclosure provides an evaluation device of a FPGA interconnection architecture based on a graph neural network, which comprises: an input unit configured to obtain description information of a target FPGA architecture and corresponding timing report information; an intra-block graph construction unit configured to obtain corresponding wiring resource graphs and global features according to the description information conversion; a node frequency label extraction unit configured to obtain frequency information of critical path node occurrence according to the timing report information; and a prediction unit configured to obtain the routability and area delay product value of the target FPGA according to the obtained wiring resource graphs and global features and the frequency information of critical path node occurrence. The evaluation device provided in some embodiments of the disclosure can predict the routability and area delay product of the interconnection architecture through the GEF model, and significantly reduce the number of calls of the traditional evaluation tool.

Electrical interconnection architectures for electrically connecting stacked prismatic battery modules in various combinations of parallel and series configurations distribute heat sources (e.g., heat conduction through a busbar and internal resistance heating from short-circuiting) to multiple battery cells rather than a single adjacent cell, thereby reducing the propagation of thermal displacement. Examples of interconnection architectures include various combinations of overlap bus and bypass bus configurations. A two-parallel module configuration can have two series submodules with cells connected in a staggered interconnection pattern. A busbar interconnection pattern can allow the negative inlet and positive outlet to be located at the same end of a battery module. Battery cells can be interconnected such that a parallel cell is not an adjacent cell.Various combinations of resistors and fuses can also be used to reduce overheating caused by short circuits.

Selective data compression for non-critical memory requests is described. In accordance with the described techniques, memory request packets are generated and communicated for retrieval of data from computer memory, and data packets including the retrieved data are communicated to a hardware compression engine. The compression engine selectively compresses the retrieved data and the compressed data is communicated through an interconnect architecture for decompression by a decompression engine. The compression of the data decreases communication congestion within the interconnect architecture. The memory request packets are configurable to include metadata providing hints to the compression engine to guide selective compression of data.

Systems and methods for an interconnect architecture for Out-of-Band (OOB) manageability in heterogeneous computing platforms. In some embodiments, an Information Handling System (IHS) may include a heterogeneous computing platform having a plurality of devices and an OOB Microcontroller Unit (MCU) integrated into the heterogeneous computing platform, where the OOB MCU is configured to: receive a command; and transmit the command or an indication of the command to a selected one of the plurality of devices via an interconnect while a host processor is in a low-power state.

A cableless radio frequency multifunctional microsystem assembly based on a vertical interconnection architecture relates to the technical field of radio frequency signal system assembly and comprises a shell, the shell is shaped with a cooling flow channel, the shell is shaped with an inner groove, the inner groove is fixed with a cover plate, the cover plate is shaped with an upper convex cover, the inner groove of the shell is fixed with a control switching module, the control switching module is fixed with a wide and narrow band TR module, the wide and narrow band TR module is fixed with a narrow band TR module, one end of the narrow band TR module is fixed with an EW switching module, and the EW switching module is located in the upper convex cover. The radio frequency interface and the low frequency interface are vertically arranged, the traditional cable interconnection between modules is replaced, the cross-layer synchronous transmission of the radio frequency signal, the control signal and the power supply is realized, and the problem of low assembly efficiency caused by complex cable layout in plane interconnection is solved.

The invention provides an FPGA interconnection architecture evaluation device based on a graph neural network, and the device comprises an input unit which is used for obtaining the description information of a target FPGA architecture and the corresponding time sequence report information; the in-block graph construction unit is used for obtaining a corresponding wiring resource graph and global features according to description information conversion; the node frequency label extraction unit is used for counting frequency information of key path nodes according to the time sequence report information; and the prediction unit is used for acquiring the accessibility and the area delay product value of the target FPGA according to the acquired wiring resource map, the global features and the frequency information of the key path nodes. The evaluation device provided in some embodiments of the disclosure can predict the accessibility and the area delay product of the interconnection architecture through the GEF model, and the calling times of a traditional evaluation tool are significantly reduced.

The invention relates to configurable architecture bandwidth throttling of workloads for GPU virtualization. One embodiment provides a graphics processor comprising: a memory interface; the graphic core cluster comprises a plurality of graphic cores; and an interconnection architecture for interconnecting a plurality of hardware clients including the plurality of graphics cores. The interconnect architecture includes a plurality of architecture ports coupled with the plurality of graphics cores. The architecture port is configured to limit bandwidth available for an associated graphics core via a bandwidth throttler circuit coupled with the architecture port.

The invention relates to a hardware architecture simulation tool oriented to system-level chip interconnection optimization, which is characterized in that a processor core, a cache controller, a memory controller and an on-chip interconnection network model with an accurate period are integrated in a full-system joint simulation framework, and the conversion between a cache consistency message and an interconnection data unit is realized through a network interface controller; network delay is fed back to a system simulation scheduler with cycle-level precision, an interconnection network adopts a router micro-architecture with an accurate cycle for modeling, key stages such as buffering, routing, virtual channel distribution, switch distribution and link traversal are finely depicted, and virtual channel flow control and a point-to-point sorting mechanism are combined, so that the routing efficiency is improved. And a power consumption analysis model based on activity counting is introduced, and the dynamic power consumption and the static leakage power consumption of the interconnection network are accurately evaluated. According to the application, various network topologies, routing strategies and hardware parameter configurations are supported, and the comprehensive influence of the interconnection architecture on the performance and energy efficiency of the chip is accurately evaluated at the system level.

A scalable multiband wavelength division multiplexing (WDM) transceiver architecture suitable for high bandwidth optical computing interconnect (OCI) between computing resources. The WDM wavelength range is divided into two or more color / wavelength bands. Each band of the WDM optical signal may be coupled by separate semiconductor optical amplifiers (SOAs) that are tuned to different bands. The wavebands may be transmitted over an optical MUX / DeMUX for transmission over an optical fiber. The optical MUX / DeMUX may include a band MUX / DeMUX or a polarization MUX / DeMUX.

In one embodiment, an apparatus includes a first integrated circuit die with metal bonding pads that are co-planar with an external surface of the die and a second integrated circuit die with metal bonding pads that are co-planar with an external surface of the die. The first and second integrated circuit dies are coupled together such that their external surfaces are in contact and the metal pads of the first integrated circuit die are in direct contact with respective metal pads of the second integrated circuit die. The apparatus also includes an inductor formed at least partially by the metal pads of the first integrated circuit die and the metal pads of the second integrated circuit die.

Methods and apparatuses are provided that can establish data links with greater bandwidths within die-to-die interconnect architectures. In one example, a system-on-a-chip (SoC) includes an error status register, a plurality of data ports for a data link, and a processor electrically coupled to the error status register and to the plurality of data ports. The processor can receive error data from the error status register and, based on the error data, can determine a portion of the plurality of data ports that are error free. Further, the processor can determine a bandwidth for the data link based on the portion of the plurality of data ports that are error free. Further, the processor can initiate a link negotiation process to establish the link with another device based on the link width value and the portion of the plurality of data ports that are error free.

Methods and apparatuses are provided to detect errors within device link sessions, and to disable the link sessions based on the detected errors. In one example, a die includes a non-transitory, machine-readable storage medium storing instructions. The die also includes at least one processor coupled to the non-transitory, machine-readable storage medium. The at least one processor is configured to execute the instructions to detect an error within a link session with a device. The at least one processor is also configured to execute the instructions to decrement an index value corresponding to the link session based on the detected error. Further, the at least one processor is configured to execute the instructions to compare the index value to a threshold value. The at least one processor is also configured to execute the instructions to disable the link session with the device based on the comparison.

The invention discloses an optical interconnection architecture, the optical interconnection architecture comprises an XPU board card, the XPU board card comprises a semiconductor chip and an optical I / O module, the optical I / O module comprises an optical driver, an optical detector array and a two-dimensional array light source, and the optical driver is electrically connected to one side of the semiconductor chip through a micro bump or direct bonding technology. The optical interconnection architecture provided by the invention has the advantages of low system complexity, short signal transmission path, low time delay and low energy consumption.

The invention belongs to the technical field of SoC design in an integrated circuit. The Crossbar interconnection architecture based on the AMBA AXI protocol comprises a top-layer interface, an arbitration system and a data distribution system, the top-layer interface comprises a slave interface and a master interface, the arbitration system comprises a decoding module and an arbiter, the decoding module comprises a write transaction channel decoder, a read address channel decoder and a read data channel decoder, and the data distribution system comprises a read transaction channel decoder, a read address channel decoder and a read data channel decoder. The data distribution system comprises a write transaction channel occupancy table, a read transaction channel occupancy table and a multi-path data selection module, wherein the read transaction channel occupancy table comprises a read address channel occupancy table and a read data channel occupancy table. Allowing the plurality of master devices to access the slave devices in parallel; as different master devices send communication requests of the same access mode to the same slave device, communication arbitration can be completed in one period; communication mechanisms such as Outstanding, out-of-order, Interleaf and the like in the AXI protocol can be supported and realized.

The invention discloses a system-on-chip interconnection architecture conflict optimization method based on pin multiplexing constraint. The method comprises the following steps: in a system-on-chip interconnection architecture, receiving a host access request and determining a target exchange switch group and a target slave; judging whether the target slave machine belongs to a multiplexing sensing type exchange switch group which is fixedly connected with peripheral equipment with a pin multiplexing relation in a design stage or not; if yes, querying a pin multiplexing controller to obtain a current activated peripheral identifier of the corresponding physical pin group; and based on the comparison result of the target slave identification and the currently activated peripheral identification and the busy / idle state of the exchange switch group, conflict awareness arbitration is executed, and the decision processing mode comprises immediate execution, execution permission, immediate rejection or suspension waiting. According to the method, the physical pin multiplexing constraint is fused into interconnection network hardware design and runtime arbitration, invalid access is actively prevented from the hardware level, the system resource utilization rate is improved, the software complexity is reduced, and the response certainty is enhanced.

Electrical interconnection architectures for electrically connecting stacked prismatic battery modules in various combinations of parallel and series configurations that distribute heat sources (e.g., heat conduction through a busbar, and internal resistance heating from short circuiting) to multiple battery cells, rather than to a single adjacent cell, thereby reducing thermal excursion propagation. Examples of interconnection architectures include various combinations of overlap bus and bypass bus configurations. A two-parallel module configuration may have two serial sub-modules with cells connected in a staggered interconnection pattern. A busbar connection pattern may allow the negative inlet and positive outlet to be located on the same end of a battery module. Battery cells may be interconnected so that a parallel cell is not an adjacent cell. Various combinations of resistors and fuses may also be used to reduce overheating from short circuiting.

The application discloses a 3D FPGA interconnection architecture based on a configurable repeater, which comprises a plurality of layers of dies; the vertical direction of the die comprises a post-wiring, a configurable repeater unit and a through silicon via in a silicon substrate region in sequence; the configurable repeater unit comprises an input selector, a mode selection and signal path, an output driver and a configuration memory, wherein the mode selection and signal path comprises three modes, which are a pass-through mode, a latching mode and a terminal mode. The application constructs a special low-delay data channel through a plurality of chips through the CRU pass-through mode, supports dynamic reconfiguration to adapt to traffic changes while significantly reducing transmission delay and area overhead, and can effectively absorb the reflection energy of unused branches to guarantee signal integrity, thereby providing a high-energy-efficiency and high-reliability interconnection solution for large-scale streaming data transmission.

The systems and methods of the present invention are used to efficiently and effectively incorporate processing power into internal memory. In one embodiment, a processing-in-memory (PIM) chip includes a memory array, logic components, and an interconnect network. The memory array is used to store information. In an exemplary implementation, the memory array includes memory cells and array peripheral components. The logic components are capable of processing the information stored in the memory array. The interconnect network is used to communicatively couple the logic components. The interconnect network may include interconnects, and a portion of the interconnects may be located in a metal layer region that is located above the memory array.

The semiconductor module includes two or more semiconductor dies and an interconnect structure coupled to the two or more semiconductor dies, the interconnect structure implementing a plurality of inter-die connection paths having a first density and a plurality of fan-out rewiring paths having a second density different from the first density.

Methods and apparatuses are provided that can establish data links with greater bandwidths within die-to-die interconnect architectures. In one example, a system-on-a-chip (SoC) includes an error status register, a plurality of data ports for a data link, and a processor electrically coupled to the error status register and to the plurality of data ports. The processor can receive error data from the error status register and, based on the error data, can determine a portion of the plurality of data ports that are error free. Further, the processor can determine a bandwidth for the data link based on the portion of the plurality of data ports that are error free. Further, the processor can initiate a link negotiation process to establish the link with another device based on the link width value and the portion of the plurality of data ports that are error free.

The present disclosure relates to non-reliable, out-of-order data transfers over a memory interconnect architecture. An inter-process communication method divides a total payload of a first memory command among a plurality of packets and encodes a last transmitted packet of the plurality of packets to include a metadata code in the total payload. The memory command can be transmitted between processes that perform a collective operation. Payloads of the packets are written to memory in a sequential address order such that the metadata code is written to a particular address and a second process generates an acknowledgement to the first memory command to the first process on a condition that the metadata code is read back from the particular address.

The application provides a multi-functional comprehensive radio frequency general vertical interconnection SoM architecture, which comprises a multi-functional comprehensive radio frequency general SoM, an interconnection structure and a SoM carrier plate; the multi-functional comprehensive radio frequency general SoM comprises a circuit architecture for radio frequency transceiving and processing; an output end of the multi-functional comprehensive radio frequency general SoM is connected with one end of the interconnection structure; the interconnection structure is an interconnection connector for transmitting radio frequency signals and digital signals; the other end of the interconnection structure is connected with an input end of the SoM carrier plate; and the SoM carrier plate comprises a radio frequency front-end circuit, a debugging connector and a network port. The application can reduce the difficulty of design and integration through the general SoM and the customized SoM carrier plate, meanwhile, the high performance and flexibility of the SoM can be enjoyed, the product life cycle management is facilitated, and the bill of materials (BOM) cost is reduced.

The invention relates to a verification method for AMBA bus matrix interconnection based on a UVM, provides a complete verification system for AMBA bus matrix interconnection, and comprises three stages: 1, constructing a verification platform, 2, constructing a test case, and 3, designing a test process. On the basis of a UVM verification methodology, a verification platform for AMBA bus matrix interconnection is built by using a VIP component of an AMBA bus. And sending a test case to the interfaces at the two ends of the master device and the slave device of the to-be-verified bus matrix interconnection architecture through the verification platform for verification. Feedback output of the bus matrix is obtained from the bus matrix interface, the verification platform collects, compares and analyzes feedback output results, and a test result is reported.