55 results about "Interconnect architecture" patented technology

Hybrid bonding interconnect (HBI) architectures for scalability. Embodiments implement a bonding layer on a semiconductor die that includes a thick oxide layer overlaid with a thin layer of a hermetic material including silicon and at least one of carbon and nitrogen. The conductive bonds of the semiconductor die are placed in the thick oxide layer and exposed at the surface of the hermetic material. Some embodiments implement a non-bonding moisture seal ring (MSR) structure.

The invention relates to the technical field of direct current motor servo drive control, and provides a Zynq AXI4 bus-based real-time transmission system and a control method thereof, and the system comprises a Zynq system on chip, a DDR3 common data area, an AXI4 bus interconnection architecture and a dynamic partition manager. By implementing the scheme, firstly, the multi-channel characteristic of the AXI4 bus is utilized, special transmission channels are distributed for different types of data, and parallel data interaction is realized; secondly, a dynamic partition manager is deployed at a PL end, a DDR3 public data area is dynamically divided into a plurality of partitions in real time according to needs, multi-task parallel is achieved, and the real-time performance of the system is improved; thirdly, the read-write operation on the DDR3 in each control period is split into a plurality of state machines through precise scheduling of the state machines, the state machines are combined into a state loop to be mounted to an AXI4 bus, it is ensured that key tasks are completed on time, and the certainty of the system is improved; fourthly, the size and the number of partitions in the DDR3 are dynamically adjusted through a dynamic partition manager, and the storage efficiency is improved.

The invention relates to the technical field of computers, in particular to a GPU cross-server interconnection system which comprises M servers and N switches, the mth server am comprises Q GPU chips, the Q GPU chips contained in any server are fixedly connected, the nth switch bn is connected with the s (n) servers, the s (n) servers are connected with the M servers, and the N switches are connected with the M servers. The s (n) servers having the connection relation with the bn form a server group corresponding to the preset topological relation. According to the system, when the server or the GPU chip breaks down, only the fault server needs to be processed, the maintenance cost is reduced, the interconnection relation of the GPU chips among multiple servers can be configured through the switch, high-bandwidth interconnection server groups with different capacities are formed, the service requirements are flexibly adapted, the flexibility of a GPU interconnection architecture is improved, and the system is suitable for large-scale popularization and application. While the high interconnection bandwidth is maintained, the switch cost and interconnection lines are saved, and the complexity of switch routing and design is reduced.

The invention belongs to the field of chip design, and provides a packet bus interconnection architecture of an SoC system, which comprises a system bus matrix SYSBUSMatrix, at least one processor bus matrix CBM, at least one high-speed peripheral bus matrix HPBM, at least one memory bus matrix RBM and one low-speed peripheral bus matrix SPBM, the CBM, the HPBM, the RBM and the SPBM are all connected with the SYSBUSMatrix through a bus bridge; the embedded processor is mounted on the CBM, and meanwhile, the CBM is connected with the RMB; a high-speed peripheral is mounted on the HPBM, and meanwhile, the HPBM is connected with the RMB; a random access memory (RAM) is mounted on the RBM, and meanwhile, the RBM is connected with the CBM and the HPBM; the SPBM is connected with a plurality of paths of AHB buses through an AXI-AHB bridge, the SPBM is connected with a plurality of paths of APB buses through an AXI-APB bridge, meanwhile, the SPBM is connected with SYSBUSMatrix, and a plurality of paths of low-speed peripherals are mounted on the AHB buses or the APB buses. According to the method, bus transmission among modules such as a processor, a high-speed peripheral and a storage can be balanced, bus competition among high-speed interfaces is effectively reduced, data transmission efficiency is improved, chip rear-end implementation is simplified, and therefore the performance of the whole SOC is optimized.

A PCB bridge, used to interconnect two or more semiconductor chips for data communication, comprises: a plurality of metal strips; and a dielectric material disposed between the plurality of metal strips. The PCB bridge is used in a vertical direction within a semiconductor module to interconnect two or more semiconductor chips. By adjusting the dielectric material and trace width of the PCB bridge, the vertical direction of the PCB bridge provides flexible impedance matching. By matching the impedance to the source, the vertical direction of the PCB bridge prevents signal reflections. The trace length of the PCB bridge is limited by the spacing between the two semiconductor chips, which further limits the inductance of the PCB bridge traces.

The application discloses a chip based on a reconfigurable neuromorphic interconnection architecture, comprising a layered dynamic reconfigurable interconnection network layer and a memristor-CMOS reconfigurable interconnection unit, and the layered dynamic reconfigurable interconnection network layer and the memristor-CMOS reconfigurable interconnection unit are dynamically adjusted in a routing path through a dynamic routing algorithm. The application has the beneficial effects that: the dynamic routing algorithm is combined with the layered dynamic reconfigurable interconnection network layer and the memristor-CMOS reconfigurable interconnection unit, thereby performing dynamic prediction of network congestion and dynamic adjustment of a routing path, and the CMOS switch and the memristor switch are connected in parallel, avoiding the limitation of traditional single devices or static interconnections, so that the network performance and reliability are improved, and the delay and power consumption of data transmission are reduced.

An interconnect fabric may comprise a plurality of interconnect routing devices (IRDs) coupled in a mesh topology via general-purpose wires that are configurable to carry different combinations of message types, and each message type may belong to a different logical channel. Each IRD may be operable to receive concurrently, from a set of input interfaces, multiple messages belonging to one or more message types. Each IRD may be operable to map the multiple messages to one or more output interfaces from a set of output interfaces based on a destination of each message. Each IRD may be further operable to send, for each of the mapped output interfaces, the messages mapped to the output interface as a combination of logical channels onto a set of general-purpose wires of the output interface, wherein each of the general-purpose wires is operable to dynamically switch between carrying messages of different message types.

The invention relates to the technical field of chips, in particular to an inter-core transmission method based on an active interposer and an interconnection structure, the inter-core transmission method based on the active interposer comprises the following steps: interacting a core logic of a functional core with a core interface, and sending a link layer data piece flit to the active interposer; analyzing the link layer data piece flit by a routing layer of the active intermediate layer, and determining a message type of the link layer data piece flit; if the message type is a data type, carrying out routing forwarding through a data plane; and if the message type is a configuration type or a message type, forwarding through a dedicated bus of a control plane. According to the technical scheme, the orthogonal architecture of combining the data plane with the control plane is adopted, the service data streams with different characteristics are separated, the interconnection architecture customization degree of respective communication networks is improved, and the efficiency is higher; meanwhile, mutual interference of configuration transmission, message transmission and data transmission is reduced, and high bandwidth of data communication and factuality of message communication are better guaranteed.

A digital signal processor (DSP) with a global and local interconnection architecture includes a plurality of DSP hardware accelerator cores each including at least one DSP module for performing a DSP operation. The DSP further includes a global interconnect for data transfer between non-adjacent ones of the DSP hardware accelerator cores and between the DSP hardware accelerator cores and processing elements external to the DSP hardware accelerator cores. The DSP further includes a local stream interconnect associated with each of the DSP hardware accelerator cores for data transfer within each core and for data transfer between adjacent ones of the DSP hardware accelerator cores.

Assemblies and methods of manufacturing assemblies comprising semiconductor chips and package substrates wherein the semiconductor chips are operably coupled to the package substrate through a solderless direct metal-to-metal bond region. The solderless direct metal-to-metal bond region also comprises a dielectric polymer. Package substrates can comprise interconnect bridges and the semiconductor chips can be operably coupled to the interconnect bridges and can also be operably coupled to each other through the interconnect bridges.

In one embodiment, an A / V interconnection architecture is provided that includes a TX A / V endpoint that supports native audio and stereo down-mixed audio on separate networks. The TX A / V endpoint outputs native audio over a video network to an RX A / V endpoint coupled to an A / V sink component that is capable of processing or outputting the native audio, and produces a stereo down-mixed version of the native audio which is output over an audio network to an audio system coupled to an audio sink component that is incapable of handling the native audio. In another embodiment, an A / V interconnection architecture is provide that enables expandable surround sound. If the number of audio channels for a type of surround sound is less than or equal to a number of local amplified output channels, surround sound is provided using only local unpowered speakers. If the number exceeds the number of the local amplified output channels, surround sound is provided using both the local unpowered speakers and one or more add on devices accessible over the audio network.

An integrated circuit communication architecture is provided and includes a clock channel, a clock divider, and a first de-skew circuit. The clock channel is configured to transmit a clock signal from the first chip to the second chip at a first rate. A clock divider is on the second chip, configured to receive the clock signal transmitted via the clock channel, and configured to create and transmit a first divided clock signal and a second divided clock signal from the received clock signal. The divided clock signal is transmitted at a reduced rate compared to the first rate. The clock divider maintains a current mode logic property of the divided clock signal. The first de-skew circuit is configured to receive and process the divided clock signal to allow sampling of data transmitted from the first chip to the second chip.

A wafer-scale compute system integrates multiple semiconductor stacks on a monolithic passive silicon substrate patterned into mechanically isolated silicon islands interconnected through through-silicon vias and redistribution wiring layers. Etched silicon spring structures provide in-plane and out-of-plane compliance, enabling wafer-scale assembly without mechanical stress. The substrate includes redundant wiring and multiple regulated power domains supplied by vertical modules. All communication between stacks occurs through the silicon substrate, forming a contiguous all-silicon computational domain with no organic circuit boards or interposers. The architecture delivers zetta-scale performance with high yield and mechanical reliability.

The invention relates to an electrical structure comprising: (a) functional modules, which are both capable of acting as transaction initiators and as transaction targets, so that a transaction initiator functional module can require a transaction target functional module to perform functions for and on its behalf; (b) a first interconnect architecture connecting the functional modules and providing communication between them; wherein the (electrical) structure is arranged such that a selected transaction initiator functional module is capable of temporarily exclusively accessing the transaction target functional module(s) performing functions for and on its behalf to ensure that transaction initiator functional modules other than the selected transaction initiator functional module cannot access it uncontrolled, wherein said selected transaction initiator functional module is a hardware security module.

The disclosure provides an evaluation device of a FPGA interconnection architecture based on a graph neural network, which comprises: an input unit configured to obtain description information of a target FPGA architecture and corresponding timing report information; an intra-block graph construction unit configured to obtain corresponding wiring resource graphs and global features according to the description information conversion; a node frequency label extraction unit configured to obtain frequency information of critical path node occurrence according to the timing report information; and a prediction unit configured to obtain the routability and area delay product value of the target FPGA according to the obtained wiring resource graphs and global features and the frequency information of critical path node occurrence. The evaluation device provided in some embodiments of the disclosure can predict the routability and area delay product of the interconnection architecture through the GEF model, and significantly reduce the number of calls of the traditional evaluation tool.

Electrical interconnection architectures for electrically connecting stacked prismatic battery modules in various combinations of parallel and series configurations distribute heat sources (e.g., heat conduction through a busbar and internal resistance heating from short-circuiting) to multiple battery cells rather than a single adjacent cell, thereby reducing the propagation of thermal displacement. Examples of interconnection architectures include various combinations of overlap bus and bypass bus configurations. A two-parallel module configuration can have two series submodules with cells connected in a staggered interconnection pattern. A busbar interconnection pattern can allow the negative inlet and positive outlet to be located at the same end of a battery module. Battery cells can be interconnected such that a parallel cell is not an adjacent cell.Various combinations of resistors and fuses can also be used to reduce overheating caused by short circuits.

Methods and apparatuses are provided to detect errors within device link sessions, and to disable the link sessions based on the detected errors. In one example, a die includes a non-transitory, machine-readable storage medium storing instructions. The die also includes at least one processor coupled to the non-transitory, machine-readable storage medium. The at least one processor is configured to execute the instructions to detect an error within a link session with a device. The at least one processor is also configured to execute the instructions to decrement an index value corresponding to the link session based on the detected error. Further, the at least one processor is configured to execute the instructions to compare the index value to a threshold value. The at least one processor is also configured to execute the instructions to disable the link session with the device based on the comparison.

Selective data compression for non-critical memory requests is described. In accordance with the described techniques, memory request packets are generated and communicated for retrieval of data from computer memory, and data packets including the retrieved data are communicated to a hardware compression engine. The compression engine selectively compresses the retrieved data and the compressed data is communicated through an interconnect architecture for decompression by a decompression engine. The compression of the data decreases communication congestion within the interconnect architecture. The memory request packets are configurable to include metadata providing hints to the compression engine to guide selective compression of data.

Systems and methods for an interconnect architecture for Out-of-Band (OOB) manageability in heterogeneous computing platforms. In some embodiments, an Information Handling System (IHS) may include a heterogeneous computing platform having a plurality of devices and an OOB Microcontroller Unit (MCU) integrated into the heterogeneous computing platform, where the OOB MCU is configured to: receive a command; and transmit the command or an indication of the command to a selected one of the plurality of devices via an interconnect while a host processor is in a low-power state.

The invention relates to a differential pair structure, a flat differential cable and an interconnection architecture, the differential pair structure comprises a pair of conductors arranged side by side, and the pair of conductors are randomly bent in the same plane along the length direction and are arranged at equal intervals. The flat differential cable comprises at least one differential pair arranged in the same plane, an insulating layer and a shielding layer, the differential pair is of a differential pair structure, the insulating layer wraps the outer side of the differential pair to fix the differential pair, an air gap extending in the bending direction is formed between each pair of conductors, and the shielding layer is arranged on the outer side of the insulating layer. The interconnection framework comprises the flat differential cable and golden fingers which are respectively connected with two ends of the flat differential cable. According to the scheme, the differential pairs are bent at will, the transmission performance is not affected by spatial layout, air gaps are reserved between the differential pairs, and the effective dielectric constant of the insulating layer is reduced.

A cableless radio frequency multifunctional microsystem assembly based on a vertical interconnection architecture relates to the technical field of radio frequency signal system assembly and comprises a shell, the shell is shaped with a cooling flow channel, the shell is shaped with an inner groove, the inner groove is fixed with a cover plate, the cover plate is shaped with an upper convex cover, the inner groove of the shell is fixed with a control switching module, the control switching module is fixed with a wide and narrow band TR module, the wide and narrow band TR module is fixed with a narrow band TR module, one end of the narrow band TR module is fixed with an EW switching module, and the EW switching module is located in the upper convex cover. The radio frequency interface and the low frequency interface are vertically arranged, the traditional cable interconnection between modules is replaced, the cross-layer synchronous transmission of the radio frequency signal, the control signal and the power supply is realized, and the problem of low assembly efficiency caused by complex cable layout in plane interconnection is solved.

One technical solution of the present invention is to provide a layout method for a scalable multi-die network-on-chip (NOC) FPGA architecture. Another technical solution of the present invention is to provide an application of the aforementioned layout method for a scalable multi-die NOC FPGA architecture. The present invention discloses a scalable multi-die NOC-based FPGA architecture and a corresponding hierarchical recursive layout algorithm designed to directly map register transfer-level dataflow designs generated by existing high-level synthesis onto the proposed interconnect architecture. The disclosed method can unlock the potential of hierarchical topologies and more effectively utilize dedicated interconnect resources, such as cross-die wire meshes, NOCs, and high-speed transceivers.

The invention discloses a chip based on a reconfigurable neuromorphic interconnection architecture, which comprises a layered dynamic reconfigurable interconnection network layer and a memristor-CMOS (Complementary Metal Oxide Semiconductor) reconfigurable interconnection unit, and the layered dynamic reconfigurable interconnection network layer and the memristor-CMOS reconfigurable interconnection unit dynamically adjust a routing path through a dynamic routing algorithm. The dynamic routing algorithm has the advantages that the dynamic routing algorithm is combined with the layered dynamic reconfigurable interconnection network layer and the memristor-CMOS reconfigurable interconnection unit, so that dynamic prediction of network congestion and dynamic adjustment of a routing path are carried out, meanwhile, the CMOS switch and the memristor switch are connected in parallel, limitation of a traditional single device or static interconnection is avoided, and the network congestion can be dynamically predicted. Not only are network performance and reliability improved, but also delay and power consumption of data transmission are reduced.

The invention provides an FPGA interconnection architecture evaluation device based on a graph neural network, and the device comprises an input unit which is used for obtaining the description information of a target FPGA architecture and the corresponding time sequence report information; the in-block graph construction unit is used for obtaining a corresponding wiring resource graph and global features according to description information conversion; the node frequency label extraction unit is used for counting frequency information of key path nodes according to the time sequence report information; and the prediction unit is used for acquiring the accessibility and the area delay product value of the target FPGA according to the acquired wiring resource map, the global features and the frequency information of the key path nodes. The evaluation device provided in some embodiments of the disclosure can predict the accessibility and the area delay product of the interconnection architecture through the GEF model, and the calling times of a traditional evaluation tool are significantly reduced.

The invention relates to configurable architecture bandwidth throttling of workloads for GPU virtualization. One embodiment provides a graphics processor comprising: a memory interface; the graphic core cluster comprises a plurality of graphic cores; and an interconnection architecture for interconnecting a plurality of hardware clients including the plurality of graphics cores. The interconnect architecture includes a plurality of architecture ports coupled with the plurality of graphics cores. The architecture port is configured to limit bandwidth available for an associated graphics core via a bandwidth throttler circuit coupled with the architecture port.

The invention relates to a hardware architecture simulation tool oriented to system-level chip interconnection optimization, which is characterized in that a processor core, a cache controller, a memory controller and an on-chip interconnection network model with an accurate period are integrated in a full-system joint simulation framework, and the conversion between a cache consistency message and an interconnection data unit is realized through a network interface controller; network delay is fed back to a system simulation scheduler with cycle-level precision, an interconnection network adopts a router micro-architecture with an accurate cycle for modeling, key stages such as buffering, routing, virtual channel distribution, switch distribution and link traversal are finely depicted, and virtual channel flow control and a point-to-point sorting mechanism are combined, so that the routing efficiency is improved. And a power consumption analysis model based on activity counting is introduced, and the dynamic power consumption and the static leakage power consumption of the interconnection network are accurately evaluated. According to the application, various network topologies, routing strategies and hardware parameter configurations are supported, and the comprehensive influence of the interconnection architecture on the performance and energy efficiency of the chip is accurately evaluated at the system level.

A scalable multiband wavelength division multiplexing (WDM) transceiver architecture suitable for high bandwidth optical computing interconnect (OCI) between computing resources. The WDM wavelength range is divided into two or more color / wavelength bands. Each band of the WDM optical signal may be coupled by separate semiconductor optical amplifiers (SOAs) that are tuned to different bands. The wavebands may be transmitted over an optical MUX / DeMUX for transmission over an optical fiber. The optical MUX / DeMUX may include a band MUX / DeMUX or a polarization MUX / DeMUX.

In one embodiment, an apparatus includes a first integrated circuit die with metal bonding pads that are co-planar with an external surface of the die and a second integrated circuit die with metal bonding pads that are co-planar with an external surface of the die. The first and second integrated circuit dies are coupled together such that their external surfaces are in contact and the metal pads of the first integrated circuit die are in direct contact with respective metal pads of the second integrated circuit die. The apparatus also includes an inductor formed at least partially by the metal pads of the first integrated circuit die and the metal pads of the second integrated circuit die.

Methods and apparatuses are provided that can establish data links with greater bandwidths within die-to-die interconnect architectures. In one example, a system-on-a-chip (SoC) includes an error status register, a plurality of data ports for a data link, and a processor electrically coupled to the error status register and to the plurality of data ports. The processor can receive error data from the error status register and, based on the error data, can determine a portion of the plurality of data ports that are error free. Further, the processor can determine a bandwidth for the data link based on the portion of the plurality of data ports that are error free. Further, the processor can initiate a link negotiation process to establish the link with another device based on the link width value and the portion of the plurality of data ports that are error free.

Methods and apparatuses are provided to detect errors within device link sessions, and to disable the link sessions based on the detected errors. In one example, a die includes a non-transitory, machine-readable storage medium storing instructions. The die also includes at least one processor coupled to the non-transitory, machine-readable storage medium. The at least one processor is configured to execute the instructions to detect an error within a link session with a device. The at least one processor is also configured to execute the instructions to decrement an index value corresponding to the link session based on the detected error. Further, the at least one processor is configured to execute the instructions to compare the index value to a threshold value. The at least one processor is also configured to execute the instructions to disable the link session with the device based on the comparison.