Method for Providing a Cluster-Wide System Clock in a Multi-Tiered Full-Graph Interconnect Architecture

Abstract

A method for providing a cluster-wide system clock in a multi-tiered full graph (MTFG) interconnect architecture are provided. Heartbeat signals transmitted by each of the processor chips in the computing cluster are synchronized. Internal system clock signals are generated in each of the processor chips based on the synchronized heartbeat signals. As a result, the internal system clock signals of each of the processor chips are synchronized since the heartbeat signals, that are the basis for the internal system clock signals, are synchronized. Mechanisms are provided for performing such synchronization using direct couplings of processor chips within the same processor book, different processor books in the same supernode, and different processor books in different supernodes of the MTFG interconnect architecture.

Description

GOVERNMENT RIGHTS[0001]This invention was made with Government support under DARPA, HR0011-07-9-0002. THE GOVERNMENT HAS CERTAIN RIGHTS IN THIS INVENTION.BACKGROUND[0002]1. Technical Field[0003]The present application relates generally to an improved data processing system and method. More specifically, the present application is directed to a method for providing a cluster-wide system clock in a multi-tiered full-graph interconnect architecture for data processing.[0004]2. Description of Related Art[0005]Ongoing advances in distributed multi-processor computer systems have continued to drive improvements in the various technologies used to interconnect processors, as well as their peripheral components. As the speed of processors has increased, the underlying interconnect, intervening logic, and the overhead associated with transferring data to and from the processors have all become increasingly significant factors impacting performance. Performance improvements have been achieved...

AI Technical Summary

Benefits of technology

[0011]Once synchronized in this manner, each of the processor chips may use the heartbeat signal it generates to provide an internal system clock. The system clock may be used by the processor chips in timing the processing of instructions with processors of the processor chips. As a result, operations being performed on each of the processor chips in each of the processor books of each of the supernodes in a computing cluster may have their operations or tasks synchronized to the same cluster-wide system clock. This results in a reduction of wasted processor cycles waiting for operations or tasks to complete on other processor chips and reduces latency in the overall computing cluster.

Problems solved by technology

As the speed of processors has increased, the underlying interconnect, intervening logic, and the overhead associated with transferring data to and from the processors have all become increasingly significant factors impacting performance.

As a result, operations which may require or benefit from synchronization of tasks being performed on the various computing devices must employ complex synchronization mechanisms, typically provided in software outside the circuitry of the computing devices.

Such synchronization mechanisms tend to cause latencies and wasted processing cycles in the computing devices as synchronization operations are performed or processors wait for other processors to become synchronized.

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