4results about How to "High speedup" patented technology

The present invention provides a power train for an automatic transmission, characterized in that a first carrier is integrated with a single pinion which meshes with a first sun gear and a first ring gear, a second carrier is integrated with the single pinion which meshes with a second sun gear and a second ring gear, and a third carrier is integrated with the single pinion which meshes with a second sun gear and a second ring gear. The third carrier and the single pinion are integrated, the single pinion is meshed with the third sun gear and the third inner gear ring, the fourth carrier and the single pinion are integrated, and the single pinion is meshed with the fourth sun gear and the fourth inner gear ring. A power assembly of an automatic transmission of the present invention transmits reverse drive of a motor through an input shaft in the same transmission path as a first gear to realize a reverse gear.

The present invention provides a device for preheating scrap steel using the waste heat of slag, comprising: a ladle, wherein the ladle contains slag; a slag pan, wherein the slag pan is inclined, wherein the ladle is located above one end of the slag pan, and wherein the ladle dumps the slag into the slag pan; a screener, wherein the screener inlet is located below the other end of the slag pan, and the slag in the slag pan slides down into the screener by itself under the action of gravity; and a spiral heat exchanger, wherein the spiral heat exchanger comprises a housing, a motor reducer, a rotating shaft, a heat exchange tube, spiral blades, a front slag baffle plate, a rear slag baffle plate, a spiral heat exchanger air inlet, a spiral heat exchanger air outlet, a spiral heat exchanger feed port, and a spiral heat exchanger slag outlet. In the present invention, the slag feed port and the slag outlet of the spiral heat exchanger should be arranged between the slag baffle plate and the rear slag baffle plate to ensure that the slag is only transported between the two baffles; a large amount of slag dust can be effectively prevented from entering the hot air circulation system, thereby reducing costs and being more conducive to environmental protection.

The invention discloses a high-parallelism programming method for a memory chip with a crossbar switch structure. The method comprises the following steps: step 1, subtracting a target matrix from an initial value of a chip to obtain a programming step length matrix of current programming; step 2, according to the characteristics of the chip and a programming task target, adjusting a single programming pulse step length, adjusting the value of the programming step length matrix, and then according to a corresponding threshold range, re-dividing the programming step length matrix to obtain a programming series matrix; step 3, using a crossbar switch splitting method to split the programming series matrix into matrixes supported by single programming of a storage chip with the minimum total splitting times, and obtaining programming row and column information according to a splitting result; and step 4, completing programming operation according to the programming row and column information obtained in the step 3. According to the invention, the programming parallelism degree of the crossbar switch structure storage chip can be improved, and the programming speed of the crossbar switch structure storage chip is accelerated.

The invention provides a sparse triangular decoupling parallel acceleration method and system for a large-scale sparse linear equation set in chip simulation, and the method comprises the steps: firstly constructing a directed dependency graph based on a non-zero structure, and completing the segmentation of an initial task; recursively applying nested subdivision to the sub-problems of which the scales exceed a preset threshold value; and meanwhile, a top-down greedy merging mechanism is introduced, and sub-problems with too small scales are aggregated. The generated sub-problems are completely decoupled and can be executed independently and parallelly, and the maximum sub-problem scale is far smaller than that of the original problem. In addition, all dependency analysis results and task division schemes can be reused across right-end terms, on the premise that the non-zero structure of the coefficient matrix is kept unchanged, one-time preprocessing can support any multiple solving tasks, and preprocessing overhead is obviously reduced. According to the scheme, on the basis that the solving precision of a direct method is completely reserved, the parallel computing potential of the multi-core processor is fully released, and the high-throughput and low-delay linear equation set solving capacity is provided for super-large-scale chip simulation.