Operator mapping method and system for coarse-grained reconfigurable architecture

A technology of architecture and mapping method, applied in the direction of program code conversion, code compilation, etc., can solve the problems of large search space, increased power consumption and area overhead of registers, long compilation time, etc., and achieve good mapping performance, small area and energy Cost-intensive, high-speedup effect

Active Publication Date: 2019-03-15
SHANGHAI JIAO TONG UNIV
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Problems solved by technology

This method based on subgraph matching has a large search space and long compilation time
Moreover, using this method requires adding a c

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  • Operator mapping method and system for coarse-grained reconfigurable architecture
  • Operator mapping method and system for coarse-grained reconfigurable architecture
  • Operator mapping method and system for coarse-grained reconfigurable architecture

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Embodiment Construction

[0062]The present invention will be described in detail below in conjunction with specific embodiments. The following examples will help those skilled in the art to further understand the present invention, but do not limit the present invention in any form. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present invention. These all belong to the protection scope of the present invention.

[0063] Such as figure 1 As shown, according to the operator mapping method of a coarse-grained reconfigurable architecture provided by the present invention, it includes:

[0064] Data flow graph generation step: generate a corresponding data flow graph (DFG) according to the intermediate language file at the front end of the compiler;

[0065] Calculation step of the minimum cycle start interval: Calculate the minimum cycle start interval according to the number of operators in the data flow graph and ...

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Abstract

The invention provides an operator mapping method and a system of a coarse-grained reconfigurable architecture, comprises a data flow graph generating step, a minimum cycle start interval calculatingstep, an operator scheduling step, a scheduling judging step, an array graph constructing step, a sorting step, a forward mapping step, a current mapping judging step, a reverse tracing step, all mapping judging steps and a configuration generating step. The invention can achieve better mapping performance in shorter compiling time, obtain higher acceleration ratio, and has smaller area and energyconsumption overhead. The ordered operator nodes are mapped forward in turn. When the forward mapping fails, a new mapping path is entered by reverse backtracking, and a successful mapping scheme isfound as far as possible without degrading the performance.

Description

technical field [0001] The invention relates to the field of computer compilers, in particular to an operator mapping method and system of a coarse-grained reconfigurable architecture. Background technique [0002] A typical application of a coarse-grained reconfigurable architecture is to speed up the execution of the innermost loop. The compiler extracts the operators of the loop body to build a data dependency graph, and then maps it to the coarse-grained PE array to execute the loop body in a soft pipeline. The machine cycle between two loops is called loop start interval II (II, Initiation Interval). The smaller the II, the faster the loop execution speed and the better the acceleration performance. One of the indicators to measure the quality of the compiler is the mapped II, and the other is the compilation time. [0003] The existing REGIMap method first constructs a compatibility graph between the data flow graph and the time-expanded PE (Process Element) array gr...

Claims

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Application Information

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IPC IPC(8): G06F8/41
CPCG06F8/45
Inventor 尹文志赵仲元绳伟光
Owner SHANGHAI JIAO TONG UNIV
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