19 results about "Loop start" patented technology

The embodiment of the application provides a control method and device of a rod wire loop device and a storage medium, the control method comprises the following steps: determining a loop starting time of the loop device according to a rolling piece running speed of a target rolling piece and a downstream rack biting time; determining a real-time loop height value according to the loop starting time, a loop starting initial height, a steady-state target loop height and a ramp rising time, and controlling the loop device to start the loop according to the real-time loop height value; acquiring a real loop height value of the loop device, and correcting an upstream rack running speed according to the real loop height value and the real-time loop height value; and when a tail of the rolling piece leaves the upstream rack, the loop device is controlled to fall back according to a tail loop closing target height. The method realizes adaptive control of the rod wire loop.

The invention discloses a starting circuit capable of being automatically turned off for a phase-locked loop oscillator, and belongs to the field of integrated circuits. The starting circuit comprises a reference current source and a starting current source; the starting current source enables a voltage-controlled oscillator in the phase-locked loop to start oscillation from an initial state, and mirror image processing is carried out on the working current of the voltage-controlled oscillator; and after the voltage-controlled oscillator reaches the preset oscillation frequency, the reference current source is used for comparison, so that the starting circuit is automatically closed, and the normal working performance of the phase-locked loop is not influenced. The circuit structure provided by the invention can ensure that the voltage-controlled oscillator starts to oscillate from the initial state of the circuit through the starting current source, and after the phase-locked loop starts to work normally, the starting circuit is automatically closed by utilizing comparison of the reference current source without influencing the normal working performance of the phase-locked loop; the problem that the phase-locked loop enters deadlock and cannot be started due to the fact that the alternating-current coupling buffer is interfered by power supply noise in the starting process of the phase-locked loop is solved.

The application discloses a PMSM sensorless starting method based on load estimation and dynamic speed regulation, and belongs to the technical field of permanent magnet synchronous motors. q0 The load torque T l0 is estimated, then the acceleration and the set value of the q-axis current are calculated according to the target speed, and finally the q-axis current is adjusted according to the input signals and the operation condition of the system, so that the high-performance dynamic speed regulation function is realized. Through the load estimation before operation and the control of the q-axis current amplitude during operation, the acceleration and the speed can be dynamically regulated in the open-loop operation, the stability of the open-loop starting is effectively improved, and the PMSM open-loop starting control under the condition of no position sensor is realized.

The invention discloses a data processing method based on a data medium table, electronic equipment and a readable storage medium. The method comprises the steps of obtaining a to-be-executed business task; the business task is constructed based on nodes selected from the data table, the business task comprises at least one loop body and conventional nodes outside the loop body, the loop body comprises a loop starting point, a loop ending point and processing nodes between the loop starting point and the loop ending point, and the processing nodes in the loop body process data according to a loop mode of the loop body; executing the business task to obtain a node operation record corresponding to each node in the business task; the node operation record comprises a node type of the node and a processing result during each time of data processing, and when the node type is a node in a loop body, the node operation record further comprises loop information of the loop body; and when at least part of the processing results are failure, re-executing at least part of the nodes in the business task based on the node operation records corresponding to the nodes in the business task. According to the scheme, the data processing efficiency and reliability can be improved.

A kind of substation secondary system based on three buses, all secondary devices in which are divided into current module, voltage module, non-electric quantity parameter module, switching value module, multi-loop starting module, multi-loop opening module, multi-loop reclosing module, multi-loop closing module according to function, each module is connected with system bus through multi-path analog switch, multi-loop integration is carried out to each module, for the part that secondary device needs to contact with primary device, all adopt wireless contact.The present application carries out large-scale high integration to all secondary systems of whole station using the integration control technology of '' one to many '', and greatly compresses the number of various secondary devices in original substation.The communication mode between primary system and secondary system is changed into wireless wide area network communication mode, so that it can be removed from existing substation, and further reduce the floor space of substation.

The present application relates to the technical field of energy storage, in particular to a network-constructed double-fed flywheel energy storage unit control loop starting and grid-connection method and system, the method comprising: starting a grid-side converter, including pre-charging a DC capacitor, and starting the grid-side converter control loop in turn according to a preset timing sequence: first starting a phase-locked loop, then starting a current loop, and finally synchronously starting a DC voltage loop and a reactive power loop; three-phase short-circuiting a double-fed motor stator, starting the flywheel and accelerating to a set speed by using a machine-side converter phase-locked loop and a network-constructed current control loop; opening the double-fed motor stator, starting the machine-side network-constructed control loop according to the timing sequence, and connecting to an AC power grid. Through the method and system, the flywheel can be directly started under network-constructed control and connected to the power grid, which is suitable for operation under weak power grid conditions and is more conducive to stable operation of the system.

The application discloses a kind of phase-locked loop frequency calibration device and method, it is related to the frequency calibration field of phase-locked loop, in which process detector sends frequency control word initial value to automatic frequency calibrator;Automatic frequency calibrator sends reset1=1 to counter according to frequency control word initial value;Phase-locked loop starts locking according to frequency control word initial value;Lock detection circuit detects the phase detection signal output by phase-locked loop after locking, and when phase detection signal is not in variation, output Lock_Done=1;Counter carries out and logic with Lock_Done with reset1, and resets, starts counting;After automatic frequency calibrator counts setting time, according to the read-back instruction of counter and the Fast signal and Slow signal determined by comparator according to the output voltage of phase-locked loop, determine calibration word.The application can reduce the error caused by phase-locked loop frequency calibration process and reduce calibration duration.

This application provides a hardware-in-the-loop (HIL) testing method and apparatus based on infinite data loop playback, comprising: acquiring a data sequence group for hardware-in-the-loop testing; determining the warm-up window, data offset time, and loop start time of the loop playback sequence to be constructed based on the data sequence group and the hardware-in-the-loop testing system, wherein the loop start time is the timestamp of the last frame data of the last data sequence in the data sequence group that has been replayed; constructing a loop playback sequence based at least on the data sequence group, the warm-up window of the loop playback sequence, the data offset time, and the loop start time; inputting the loop playback sequence into the hardware-in-the-loop testing system for data loop testing processing of the domain controller under test, and obtaining test results. This solves the problem that existing HIL testing data backfeeding schemes have limited backfeeding data volume, which cannot meet the requirements of long-term continuous testing.

The present disclosure provides a task processing method and system, an electronic device, and a storage medium, which are applied to a front-end unit in a graphics processor. The front-end unit includes an instruction execution unit, an instruction acquisition unit, and a plurality of counters. The method includes: acquiring, by the instruction acquisition unit, a target loop execution task generated by a central processing unit; assigning a value to a target counter and executing instructions in an instruction queue of the target loop execution task in sequence from an (i+1)th instruction, by the instruction execution unit, in a case where it is determined that an ith instruction is a loop start instruction; and determining whether a loop end condition is met according to a current value of the target counter in a case where it is determined that an (i+j)th instruction is a loop end judgment instruction, and jumping to the (i+1)th instruction and continuing loop execution until the loop end condition is met. According to embodiments of the present disclosure, the task processing efficiency can be improved.

The present invention proposes a loop branch prediction instruction fetching device, processor, and electronic device. A reference unit generates a reference address based on acquired address data; an instruction storage unit reads a historical reference address for prefetching. When an instruction storage unit hits, the target instruction corresponding to the historical reference address is transmitted to a first branch predictor after K clock cycles. The first branch predictor is configured to read the historical reference address, perform address prediction based on the historical reference address and its corresponding target instruction, and provide the predicted address to the reference unit. A second branch predictor is configured to read the historical reference address and, if the historical reference address is the same as the loop end address stored therein and the number of pending loops is greater than 0, provide the stored loop start address to the reference unit. Reducing the number of instructions required to maintain loop variables and judgment conditions can reduce code complexity and maintenance difficulty, improve instruction fetching efficiency, and fully realize the performance potential of the processor.

The invention provides a switch current limiting circuit and an electronic product, and the circuit comprises the steps: reducing the current of a switch driving tube at a certain ratio through a current mirror image mode, and transmitting the current to a current detection module; the current detection module reduces the current according to a certain proportion and converts the current into sampling voltage; and the sampling voltage is compared with the reference voltage generated by the current-limiting adjusting module, and the gate voltage of the switch driving tube is controlled based on the comparison result. And when the current of the switch driving tube is lower than the current limiting value, the sampling voltage is lower than the reference voltage, the gate voltage of the switch driving tube is at a higher potential, and the switch driving tube works in a linear region and is normally switched on and off. When the current flowing through the switch driving tube reaches or is close to a current limiting value, the negative feedback loop starts to work, and the purpose of current limiting is achieved. According to the switch current limiting circuit and the electronic product, the current limiting function can be achieved when the switch driving tube works in the linear region and the saturation region, the switch driving tube is effectively protected, and the chip safety is improved.

The embodiment of the invention discloses an audio transmission method and device, a computer, a storage medium and a program product, and the method comprises the steps: generating a loop start instruction when audio data in a cloud game application is transmitted to business equipment, and sequentially transmitting the loop start instruction and a loaded first audio clip to the business equipment; when the duration of the sent first audio clip is the one-way audio length, sending a data ending instruction to the service equipment; the data ending instruction is used for circularly playing the first audio clip when the service equipment does not receive a loop ending instruction; and when detecting that the loop is ended, sending a loop ending instruction to the service equipment, so that the service equipment ends playing the first audio clip based on the loop ending instruction. According to the invention, the traffic generated by audio transmission can be reduced.

The application discloses a loop control method and system based on RISC-V extension, and self-defines a loop control instruction in a main operation code and instruction coding space reserved by RISC-V; a fetch instruction module, a decoding module, a state control register and a hardware loop control module are designed, the decoding module writes loop information into the state control register, the hardware loop control module reads the loop information from the state control register, and arbitration is performed in combination with a control signal of the decoding module and an instruction address; when a current address does not reach a loop end, an enabling signal is sent to make the fetch instruction module fetch instructions in sequence; when the current address reaches a last instruction of a loop segment and a loop number is not zero, a loop start address is sent to the fetch instruction module to make it continue to loop, and a conditional jump instruction for existing loop judgment is saved; for an assembly instruction part for loop control, the assembly instruction part is replaced by the loop control instruction extended by the application, and performance loss caused by a loop program can be effectively reduced.

The invention discloses a WASM smart contract bytecode loop vector optimization method suitable for hardware acceleration, and aims to solve the problems that in a block chain scene, a smart contract exists in a WASM bytecode form, and an existing optimizer does not support loop optimization starting from the WASM bytecode, the optimization of Pass is expanded in a Binaryen framework, and the optimization of the WASM bytecode is realized. By combining formalized constraint verification and runtime check, a single-layer linear loop is converted into a single-instruction multi-data SIMD instruction, the theoretical 4-time speed-up ratio is achieved, and meanwhile semantic equivalence and runtime safety are ensured. The method comprises four core layers, namely an analysis input layer, a protocol preprocessing layer, a constraint condition verification layer and an optimization generation layer, wherein the constraint condition verification layer and the optimization generation layer are realized through a five-stage optimization Pass based on a Binaryen framework. According to the method, the execution efficiency of the intelligent contract containing the high-frequency linear single cycle is remarkably improved, the method is suitable for optimization preprocessing before block chain transaction execution, the execution speed of the intelligent contract can be improved, and the overall performance of the block chain is improved.

A memory device includes memory cells connected to word lines. The memory cell is disposed in the memory hole and is configured to maintain a threshold voltage corresponding to a data state. The memory holes are organized into rows grouped in a string comprising each of a plurality of blocks. A control component is configured to acquire a smart verify program voltage by programming the memory cells connected to one of the word lines and associated with one of the strings in a smart verify operation, the smart verify operation including a plurality of smart verify loops starting with an initial program voltage. The initial program voltage is adjusted based on a cycling condition of the memory cell. The control component is further configured to program at least some of the memory cells connected to the word line in a program operation using the smart verify program voltage based on the adjusted initial program voltage.

The invention discloses a configurable delay circuit, and relates to the technical field of asynchronous circuit design. The configurable delay circuit comprises a cycle starting module, a cycle module and a cycle judgment module, and the cycle starting module is used for receiving a to-be-delayed signal and outputting a cycle starting signal based on the to-be-delayed signal; the circulation module is used for outputting a circulation judgment starting signal based on the circulation starting signal; the cycle judgment module is used for receiving the delay period signal, determining the number of times of delay based on the delay period signal, delaying the cycle judgment starting signal based on the number of times of delay and then outputting a cycle ending judgment signal; the circulation module is also used for outputting a circulation response signal based on the circulation ending judgment signal; and the cycle starting module is also used for resetting the cycle starting signal based on the cycle response signal, overturning the current signal and outputting a delayed signal. According to the circuit, the delay time can be dynamically adjusted, and the complexity of the circuit structure can be reduced.

This invention discloses a collaborative communication and safety control method and system for a heterogeneous robot controller. The method includes the following steps: deploying a communication middleware based on Micro XRCE-DDS on an MCU module, configuring Quality of Service (QoS) policies for heartbeat, power status, and emergency stop messages respectively; during system power-on, establishing a dual-channel closed-loop start-up control mechanism combining hardware start-up gating and software readiness confirmation; during system operation, the MCU module collects the bus voltage, motor phase current, and motor speed parameters of the joint modules in real time, and when an emergency stop trigger signal is received, selects different deceleration strategies to execute braking control based on the parameters; and achieves physical-level safety isolation in the event of a main control module failure. This invention solves the technical problems of high communication latency, unreliable state synchronization, chaotic start-up timing, and delayed fault response in traditional communication methods.

The invention relates to the technical field of energy storage, in particular to a control loop starting and grid-connected method and system for a grid-forming type doubly-fed flywheel energy storage unit, and the method comprises the steps: starting a grid-side converter, including pre-charging a direct-current capacitor, and sequentially starting a control loop of the grid-side converter according to a preset time sequence: firstly starting a phase-locked loop, then starting a current loop, and starting the phase-locked loop; finally, the direct-current voltage loop and the reactive loop are synchronously started; the stator of the doubly-fed motor is in three-phase short circuit, and a machine-side converter phase-locked loop and a network-forming current control loop are adopted to start a flywheel and accelerate to a set rotating speed; the stator of the doubly-fed motor is open-circuited, and a machine-side network-constructing control loop is started according to a time sequence and is connected to an alternating-current power grid. Through the method and the system, the flywheel can be directly started and accessed to the power grid under the control of a constructed network, the method is suitable for operation under a weak power grid working condition, and stable operation of the system is facilitated.

This invention belongs to the field of closed-loop fiber optic gyroscope control, specifically relating to a method for adaptive switching of the operating mode of a closed-loop fiber optic gyroscope control circuit. Through serial communication between a host computer and the closed-loop fiber optic gyroscope control circuit, it enables control of the number of light intensity signal sampling points, the first closed-loop gain, the second closed-loop gain, the first closed-loop start delay, the second closed-loop start delay, the initial values ​​of the X-axis second closed-loop, the Y-axis second closed-loop, the Z-axis second closed-loop, the scale factor, the pulse equivalent and pulse width, and mode verification control parameters. By adding the control parameters stored in EEPROM and comparing them with preset standard values, the operating mode of the closed-loop fiber optic gyroscope control circuit is adaptively determined, adapting to different production stages of gyroscope control electronics and achieving verification purposes. Without modifying the programmable logic device software of the closed-loop fiber optic control circuit, it can quickly read, write, and verify control parameters, improving efficiency and fault tolerance.