115 results about "Loop start" patented technology

A system is disclosed for programming non-volatile storage that improves performance by setting the starting programming voltage to a first level for fresh parts and adjusting the starting programming voltage as the memory is cycled. For example, the system programs a set of non-volatile storage elements during a first period using an increasing program signal with a first initial value and subsequently programs the set of non-volatile storage elements during a second period using an increasing program signal with a second initial value, where the second period is subsequent to the first period and the second initial value is different than the first initial value.

The invention discloses a starting circuit and a starting method of a permanent magnet synchronous motor. The starting circuit of the permanent magnet synchronous motor comprises an inverter circuit, three current sensors, a motor and a master control panel, wherein the inverter circuit comprises three groups of IGBT modules; the three groups of IGBT modules are electrically connected with the motor through three leads respectively; the three current sensors are respectively located on the three leads; and the master control panel comprises a rotating speed control module, a starting current instruction generation module, a current control module, a rotating speed estimation unit, an integrator unit, a position signal switching unit, an IPARK unit, a CLARK unit, a PARK unit and an SVPWM unit. The starting circuit and the starting method have the characteristics that the starting process can be quickened; the angle difference between a given rotating coordinate system and an actual rotating coordinate system is reduced; and smooth switching from rotating speed open loop starting to double closed-loop sensorless vector control operation of rotating speed current is ensured.

Instruction set techniques have been developed to identify explicitly the beginning of a loop body and to code a conditional loop-end in ways that allow a processor implementation to efficiently manage an instruction fetch buffer and/or entries in an instruction cache. In particular, for some computations and processor implementations, a machine instruction is defined that identifies a loop start, stores a corresponding loop start address on a return stack (or in other suitable storage) and directs fetch logic to take advantage of the identification by retaining in a fetch buffer or instruction cache the instruction(s) beginning at the loop start address, thereby avoiding usual branch delays on subsequent iterations of the loop. A conditional loop-end instruction can be used in conjunction with the loop start instruction to discard (or simply mark as no longer needed) the loop start address and the loop body instructions retained in the fetch buffer or instruction cache.

The embodiment of the invention provides a construction method and device for a double-layer path of a vehicle-mounted unmanned aerial vehicle. The method comprises the steps that cluster grouping isperformed according to a minimum distance of a task target point space of the unmanned aerial vehicle, and a Hamilton path conforming to unmanned aerial vehicle cruising ability constraint of each group is constructed; and the Hamilton paths corresponding to all the groups are merged and adjusted through a connection algorithm, and a loop starting from a base point through a starting point and anending point of each Hamilton path back to the base point is constructed. Through the method, a double-layer path planning scheme of the vehicle-mounted unmanned aerial vehicle during cooperative collection of target information is quickly established, it is guaranteed that the vehicle-mounted unmanned aerial vehicle travels by one loop in a path network within a planning area, the unmanned aerialvehicle completes collection of information at all task target points, and working efficiency is greatly improved.

A method, system or computer usable program product for providing alerts of inefficiency of an environmental conditioning system including, responsive to a cycle initiation by the environmental conditioning system, measuring a difference between an intake temperature and an outlet temperature after a predetermined period of time, and responsive to the difference being below a minimum level, generating an alert.

The invention relates to an air source heat pump system, which comprises two injection enthalpy-increasing air source heat pump subsystems and two triple-sleeve heat exchangers. A refrigerating loop starts from an outlet of an indoor heat exchanger of each subsystem, runs through a flow regulating valve and enters a suction opening of a compressor via the triple-sleeve heat exchanger, a first throttling valve, an outdoor heat exchanger and a first gas and liquid separator of the subsystem; and an air supplementing loop is branched at the outlet of the indoor heat exchanger of each subsystem and enters an air supplementing opening of the compressor of the subsystem via a second throttling valve, the triple-sleeve heat exchanger and a coupling subsystem triple-sleeve heat exchanger of the subsystem. By the aid of the coupling injection enthalpy-increasing air source heat pump system, problems that heat cannot be supplied continuously during defrosting in a low-temperature environment and defrosting time is long are solved, energy is reasonably utilized, heat required by defrosting is increased, and problems that the quantity of accumulated liquid refrigerating working media generated by an outdoor heat exchanger of a defrosting subsystem is increased, a compressor is impacted by liquid and the like are solved.

The invention discloses a starting method of a senseless permanent magnet synchronous motor, comprising the following steps: S10), after short-circuiting a motor winding, detecting a motor induced current by driving a sampling module of a controller; S20), determining whether the motor induced current is less than a predetermined value of induced current, if so, proceeding to step S30), or if not,proceeding to step S40); S30), performing open-loop start control; S40), determining whether the motor is in a forward or reverse rotation state, if in the forward rotation state, proceeding to stepS50), if not, proceeding to step S60); S50), performing forward rotation closed-loop vector start control; and S60), performing reverse rotation closed-loop vector start control. The starting method ensures the fast and low-current high-efficiency start when the permanent magnet synchronous motor is stationary or tends to be stationary, realizes fast closed-loop vector control under strong downwind or upwind conditions, reduces energy consumption, shortens start time, and makes motor start smooth.

A highly efficient protection path bandwidth management method is provided. When a protection path is set up in a loop with a node A as the starting point and endpoint in order to protect a working path, the bandwidth of the protection path is changed by transferring a bandwidth change request message, containing the identifier of the protection path as well as the value of the bandwidth after the change, so as to cycle once around the protection path set up in a loop starting from a node B that first received a PATH message for a working path.

A data processing apparatus adopting a pipeline processing system, includes an instruction memory which store instruction packets; and a processing unit configured to execute the instruction packets sequentially in a pipeline manner. The processing unit includes an instruction queue and a loop speed-up circuit. The instruction packets stored in the instruction queue are executed sequentially by the processing unit. The loop speed-up circuit stores the instruction packets read out from the instruction memory into the instruction queue sequentially, holds the instruction packet containing a loop start address for a loop process, and outputs the held instruction packet to the instruction queue, when a loop process end is detected and the loop process is not circulated for a predetermined number of times.

A processor includes an instruction fetch unit providing a fetch address to the memory system; a branch buffer, a normal buffer, and a general buffer, which receive fetch instructions, respectively; a to-be-issued instruction selecting unit, which selects an instruction from the normal buffer, the branch buffer, and the general buffer and issues the instruction in conformity with an instruction from the instruction buffer control unit; an instruction decoding unit, which receives the instruction issued from the to-be-issued instruction selecting unit, decodes the issued instruction, and transmits decoded results to the instruction buffer control unit; a loop processing unit, which receives the decoded results from the instruction decoding unit and transmits a loop start address to the instruction fetch unit; and a branch determination unit, which transmits a fetch address to the instruction fetch unit established when a branching condition is satisfied or not satisfied.

A system employing a resonating device and a controller implements a method involving an establishment by the controller of open-loop oscillations of the resonating device at a resonating frequency of the resonating device, and an establishment by the controller of closed-loop oscillations of the resonating device based on the open-loop oscillations of the resonating device at the resonating frequency. To this end, the controller controls an application and a tuning of a first open-loop drive signal to the resonating device based on a design-drive standard resonating frequency range whereby the controller can measure and designate a frequency of a resonating output signal from the resonating device as a calibration resonant frequency, and controls an application and a tuning of a second open-loop drive signal to the resonating device based on the calibration resonant frequency whereby the controller can subsequently apply a closed-loop drive signal to the resonating device.

The invention relates to a temperature control method for equipment on a satellite in a system level thermal vacuum test. The method mainly includes a temperature range determining method for the equipment on the satellite, a high temperature determining method for the equipment on the satellite, an infrared heating cage manufacturing method before the test, a method for modifying the on-off state and the working state of the equipment on the satellite in the test process and an active temperature control heating loop starting/stopping threshold on the satellite, and a loop controlling method. According to the method, when the infrared heating cage is used for simulation based on external heat stream, temperature control of the equipment on the satellite is reasonable and effective, the temperature changing rate of the equipment on the satellite is increased, it is guaranteed that the temperature of the equipment does not exceed the checking and accepting level temperature range, and not only is the safety of the equipment on the satellite guaranteed, but also the purpose of eliminating potential early-stage defects of the satellite is effectively achieved.

The invention relates to an escalator control system, in which communication is realized by a pair of twisted-pair lines between a principal board and subordinate boards and by setting the principal board and the subordinate boards, wherein, the subordinate boards receive the nearby input signal and send the signal to the principal board through a CAN bus; an upper subordinate board and a lower subordinate board send the display information transmitted from the principal board to a key switch box to display; the principal board inspects the input signal, determines the output signal through logical operation, records the fault of the error signal and alarms; a starting point of a safety loop starts from the principal board, goes through a series of safety switches, connects the upper subordinate board and the lower subordinate boards nearby, goes through an end point of the principal board and returns to the principal board, the principal board checks the state of the safety loop and realizes control and detection of multiple functions of the escalator. The escalator control system, as an ideal substitute of the prior art, avoids laying transmission lines in large quantity and has the advantages of simple structure, reasonable layout, safe and reliable system operation and braking and effectively reduced production cost.

A delay addressed data path register file is designed for use in a programmable processor making up a cell in a multi-processor or array signal processing system. The delay addressable register file is particularly useful in, inter alia, adaptive filters where the filter update latency is variable, interpolation filters where the interpolation factor needs to be programmable, and decimation filters where the decimation factor needs to be programmable. The programmability is achieved in an efficient manner, reducing the number of cycles required to perform this task. A single parameter, the “delay limit” value, is programmed at start-up, setting up an internal delay-line within the register file of the processor. Thus, any of the delayed registers can be addressed by specifying the delay index during run-time. The delay line advances one location, modulo “delay-limit”, when the processing loop starts a new iteration.

A technique for reducing or eliminating the access charges typically payable by an IXC to a LEC, and, in turn, payable by the subscriber to the IXC, for originating long distance calls by providing a hardwire connection between the IXC and the customer premises. The hardwire connection is created by purchasing analog facilities from the LEC which originate at the Central Office and connecting these facilities directly to a Central Office D4 multiplexer. The terminating end of the analog facilities are installed at the subscriber premises and terminated on a standard RJ11X four wire jack. The voice interface modules typically used in the D4 multiplexer are replaced by Foreign Exchange Subscriber (FXS) modules which perform A/D conversion of the analog voice data provided over the analog facilities from the customer premises. A T1 or higher capacity digital facility is also ordered from the LEC to terminate to the Central Office D4 multiplexer, and the T1 or higher capacity digital facility is D4/AMI configured for 56 kbps DS0 channels. The terminating end of the T1 or higher capacity digital facility is directed to a tandem "toll" Central Office and is terminated on a K01 digital electronic cross-connect system (DEXCS) frame which is ordered from the LEC. Each of the channels of the T1 or higher capacity digital facility is then configured by the customer using a network reconfiguration service at the end pointing towards the Central Office D4 multiplexer with Foreign Exchange Office (FXO) Loop Start signaling. A T1 is also ordered from the LEC to connect the DEXCS to the IXC and is also D4/AMI configured for 56 kbps DS0 channels. Each of the channels of this T1 is also configured by the customer using the reconfiguration service at the end pointing towards the IXC with FXS Loop Start signaling. The IXC terminates the T1 from the DEXCS within its own Call Control Platform.

The invention discloses an air conditioner, a compressor, and a closed-loop zero-speed start method and system for the compressor. The method comprises the following steps: injecting a high-frequency voltage signal to the compressor when the compressor is started, so as to estimate the initial position of a compressor rotor; carrying out the initialization of a magnetic flux observer and a phase locking ring of the compressor according to the initial position of the compressor rotor; estimating the real-time position of the compressor rotor through the initialized magnetic flux observer and phase locking ring after the compressor enters a closed-loop control state, so as to carry out the vector control of the compressor. The method can achieve the full-process position closed-loop start of the compressor, can reduce the amplitude of the start current of the compressor, and achieves an effect of energy consumption reduction.

The invention relates to the technical field of solid state power amplifiers, and discloses an over excitation protection circuit of a solid state power amplifier. The over excitation protection circuit specifically comprises an automatic level control loop and a switch control loop. A threshold of the automatic level control loop is set to stabilize over excitation input power at a certain rated power level; and a time delay or a threshold of the switch control loop is set to turn on a radio frequency switch after the automatic level control loop starts to control, so as to prevent an over excitation signal prior to control from entering a radio frequency amplification link. By means of the cooperative use of the two circuits, when an over excitation signal is input, subsequent equipment is protected, and meanwhile, the amplitude of the input over excitation signal is controlled instead of simply preventing over excitation by the on-off of a time delay switch used in the prior art. A universal over excitation protection device limiter is not used in the over excitation protection circuit disclosed by the invention, thereby avoiding the deterioration of such indexes as transmission system harmonics, third-order cross modulation, noise coefficient and the like. The invention further discloses an implementation method of over excitation protection circuit of the solid state power amplifier.

A loop control circuit of the present invention includes a program counter for sequentially indicating an address of an instruction, a LSA calculation circuit for calculating a loop start address of a loop start instruction, a LEA calculation circuit for calculating a loop end address of a loop end instruction, an interlock generation circuit for generating an interlock until a pipeline of a loop instruction is completed so as to suspend a pipeline process of the loop end instruction, and a loop end evaluation circuit for setting the program counter to the loop start address according to a result of a comparison between the program counter and the loop end address after the pipeline process of the loop instruction is completed.