52results about "Systolic arrays" patented technology

A data stream processing unit (DPU) and method for use are provided. A DPU includes a number of processing elements arranged in a sequence, and each datum in the data stream visits each processing element in sequence. Each processing element has a memory circuit, data and metadata input and output channels, and a computing circuit. The metadata input represents a partial computational state that is associated with each datum as it passes through the DPU. The computing circuit for each processing element operates on the data and metadata inputs as a function of its position in the sequence, producing an altered partial computational state that accompanies the datum. Each computing circuit may be modeled, for example, as a finite state machine, and the collection of processing elements cooperate to perform the computation. The computing circuits may be collectively programmed to perform any desired computation.

A general matrix-matrix multiplication (GEMM) dataflow accelerator circuit is disclosed that includes a smart 3D stacking DRAM architecture. The accelerator circuit includes a memory bank, a peripheral lookup table stored in the memory bank, and a first vector buffer to store a first vector that is used as a row address into the lookup table. The circuit includes a second vector buffer to store a second vector that is used as a column address into the lookup table, and lookup table buffers to receive and store lookup table entries from the lookup table. The circuit further includes adders to sum the first product and a second product, and an output buffer to store the sum. The lookup table buffers determine a product of the first vector and the second vector without performing a multiply operation. The embodiments include a hierarchical lookup architecture to reduce latency. Accumulation results are propagated in a systolic manner.

A linear systolic array is added to the lower side of a trapezoid systolic array created by combining a triangular systolic array and a square systolic array. In order to make the connection among the cells fixed, the intermediate result output from each row of the trapezoid systolic array to a lower row is shifted in phase with respect to the intermediate result of the complex MFA algorithm, the phase shift is absorbed by the next row, and the phase shift in the intermediate result output from the last row of the trapezoid systolic array is corrected by the linear systolic array. Each cell is implemented by a CORDIC circuit that processes vector angle computation, vector rotation, division, and multiply-and-accumulate with a constant delay.

When a plurality of reference signal series are handled with the same input signal series during processing of an RLS algorithm based on QR decomposition, an object is to handle the plurality of reference signal series simultaneously. When performing processing of a sequential least-squares algorithm based on QR decomposition, to a configuration comprising a plurality of boundary cells (empty circles) which calculate appropriate rotation parameters for transformations based on Givens rotation, a plurality of internal cells (squares) which cause rotation of elements of a received data vector using the calculated values of the boundary cells (empty circles), and a final cell (double circles) which derives the a posteriori estimated error from the calculated values of the boundary cells (empty circles) and internal cells (squares), additional internal cells (squares) within 21 are connected so as to receive signals output from each of the internal cells (squares) arranged in the end cell column to which the signal series is input, and to the final cell (double circles) is connected an additional final cell (double circles) within 21, so as to receive the calculated values from the boundary cells (empty circles) and the calculated values from the additional internal cells (square) input to the additional final cell (double circles).