Sparse neural network processor based on systolic array

Abstract

The invention provides a sparse neural network processor based on a systolic array. The sparse neural network processor comprises a storage unit, a control unit, a sparse matrix operation array, a calculation unit and a confluence array. The storage unit is used for storing weights, gradients, features and instruction sequences used for scheduling data streams. The control unit takes out data required by the training and reasoning process from the storage unit according to the control of the instruction sequence, converts the data into a sparse matrix operation format and sends the data into the sparse matrix operation array. The sparse matrix operation array comprises a plurality of processing units connected in a systolic array mode and is used for completing sparse matrix operation. Thecalculation unit is used for completing element-by-element operation such as a nonlinear activation function. The confluence array delivers the same data segment to different rows of the systolic array through internal data transfer to reduce storage overhead. The processor makes full use of the sparsity of the weight and the characteristics, achieves the improvement of the speed and power consumption ratio in the neural network training and reasoning process, and has the advantages of high concurrency, low bandwidth requirements and the like.

Description

technical field [0001] The invention relates to neural network technology and computer architecture, in particular to computer architecture for sparse neural network calculation. Background technique [0002] In recent years, deep learning has gradually achieved more and more remarkable results in fields such as image recognition and speech processing. However, as the depth of the network continues to increase, the computing power and memory access bandwidth required in the training and inference process of the deep neural network are gradually difficult to be met by traditional computing platforms. Therefore, various domain-specific architectures (domain specified architectures) applied to neural networks have been proposed by the industry and academia to meet this requirement. Among them, the systolic array architecture has attracted great attention from the industry and academia due to its characteristics of high concurrency and low bandwidth requirements. [0003] On t...

AI Technical Summary

Problems solved by technology

However, it is worth noting that due to the irregularity of the sparse patterns of neural network weights, gradients, and features, this sparsity of neural networks is often difficult to be effectively utilized, especially on highly regular computing platforms such as systolic arrays.

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