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Deep learning implementations using systolic arrays and fused operations

An opcode, source matrix technique applied in the field of computer processor architecture

Pending Publication Date: 2021-03-26
INTEL CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] Unfortunately, the widespread adoption and application of deep learning-based machine learning systems faces challenges related to computational requirements, power consumption, and memory bandwidth utilization

Method used

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  • Deep learning implementations using systolic arrays and fused operations
  • Deep learning implementations using systolic arrays and fused operations
  • Deep learning implementations using systolic arrays and fused operations

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Embodiment Construction

[0059] In the description that follows, numerous specific details are set forth. However, it is understood that the embodiments may be practiced without these specific details. In other instances, well-known circuits, structures and techniques have not been shown in detail in order not to obscure the understanding of this description.

[0060] References in the specification to "one embodiment," "an embodiment," "an example embodiment," etc., indicate that the described embodiment may include a particular feature, structure, or characteristic, but that each embodiment may not necessarily include that particular feature. , structure or characteristic. Additionally, such phrases are not necessarily referring to the same embodiment. In addition, when a particular feature, structure or characteristic is described in connection with one embodiment, it is considered to be within the knowledge of those skilled in the art to implement such feature, structure or characteristic in con...

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Abstract

Disclosed embodiments relate to deep learning implementations using systolic arrays and fused operations. In one example, a processor includes fetch and decode circuitry to fetch and decode an instruction having fields to specify an opcode and locations of a destination and N source matrices, the opcode indicating the processor is to load the N source matrices from memory, perform N convolutions on the N source matrices to generate N feature maps, and store results of the N convolutions in registers to be passed to an activation layer, wherein the processor is to perform the N convolutions andthe activation layer with at most one memory load of each of the N source matrices. The processor further includes scheduling circuitry to schedule execution of the instruction and execution circuitry to execute the instruction as per the opcode.

Description

technical field [0001] The field of the invention relates generally to computer processor architecture, and more specifically to implementations of deep learning using systolic arrays and fused operations. Background technique [0002] Matrices are increasingly important in many computational tasks such as machine learning and other massive data processing. Deep learning architectures, such as deep neural networks, have been applied to areas including computer vision, speech recognition, natural language processing, audio recognition, social network filtering, machine translation, bioinformatics, and drug design. [0003] Unfortunately, the widespread adoption and application of deep learning-based machine learning systems faces challenges related to computational requirements, power consumption, and memory bandwidth utilization. For example, deep learning neural network models can be many megabytes in size and require millions of arithmetic operations per second to process...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/38G06F9/30G06N3/04G06N3/063
CPCG06F9/3867G06F9/382G06F9/3836G06F9/30098G06N3/063G06N3/045G06N3/084G06F9/30036G06F17/153G06F9/3001G06N3/048G06F9/3802G06F9/3818G06F15/8046G06N3/04G06N3/08
Inventor 威廉·拉什苏布拉马尼亚姆·迈尤兰瓦格斯·乔治布雷特·L·托尔拉杰什·桑卡兰罗伯特·查佩尔萨普拉蒂姆·帕尔亚力山大·F·海涅克埃尔莫斯塔法·乌尔德-艾哈迈德-瓦尔陈刚
Owner INTEL CORP
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