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Processing method and apparatus for implementing systolic arrays

A technology of systolic array and processing equipment, applied in the direction of systolic array, electrical digital data processing, digital data processing components, etc., can solve the problems of impractical implementation of VLIW, complex structure, etc.

Inactive Publication Date: 2005-07-27
KONINKLIJKE PHILIPS ELECTRONICS NV
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Problems solved by technology

Furthermore, the need for move units to access the same registers that need to be accessed by other functional units introduces structural complexity in the VLIW design
All this makes a VLIW implementation of a systolic array impractical

Method used

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  • Processing method and apparatus for implementing systolic arrays
  • Processing method and apparatus for implementing systolic arrays
  • Processing method and apparatus for implementing systolic arrays

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Embodiment Construction

[0022] exist image 3 in, refactored figure 2 of systolic arrays to enable their implementation in VLIW architectures. Outgoing slots I1 to I4 are made explicit and a first-in-first-out (FIFO) delay line comprising register R is maintained at the input of a functional unit (eg, ALU). Dashed boxes represent physical registers that are available in hardware but are not used in the systolic configuration shown. The technical solution thus delineated suggests a VLIW template that can efficiently map systolic structures. By providing a distributed register file on each input of a functional unit FU, it is possible to generalize image 3 The intuitive concept shown in .

[0023] Figure 4 A programmable processor architecture is shown as a preferred embodiment of a VLIW template that can efficiently map systolic structures. In particular, one distributed register file DCF is provided for each input of each functional unit FU. Furthermore, an interconnection network consistin...

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Abstract

The present invention relates to a processing method and apparatus for implementing a systolic-array-like structure. Input data are stored in a depth-configurable register means (DCF) in a predetermined sequence, and are supplied to a processing means (FU) for processing said input data based on control signals generated from instruction data 5 wherein the depth of the register means (DCF) is controlled in accordance with the instruction data. Thereby, systolic arrays can be mapped onto a programmable processor, e.g. a VLIW processor, without the need for explicitly issuing operations to implement the register moves that constitute the delay lines of the array.

Description

technical field [0001] The present invention relates to a processing method and equipment, in particular to a scalable VLIW (Very Large Instruction Word) processor or a coarse-grained reconfigurable processor for realizing a systolic array structure. Background technique [0002] A programmable or configurable processor is a prefabricated device that can be customized after manufacture to perform specific functions according to instructions or configurations respectively given to it. These instructions or configurations, when executed in a processor, control processor resources (e.g., arithmetic logic unit (ALU), register file, interconnect, memory, etc.) perform some action. In general, a configurable processor will perform more operations spatially than a programmable processor, and a programmable processor will perform more operations temporally than a configurable processor. [0003] An algorithm-to-silicon design methodology for digital signal processors (DSPs) has no...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/38G06F15/80H04B1/00
CPCG06F15/8046G06F7/00
Inventor B·德奥里维拉卡斯特鲁普佩
Owner KONINKLIJKE PHILIPS ELECTRONICS NV
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