10results about How to "Improve parallel efficiency" patented technology

The invention provides a system architecture for cross-data center large model training and a resource allocation method and system, and belongs to the technical field of cross-wide area distributed large model training. According to the method, large-scale model cooperative training across multiple data centers can be realized, and the bottleneck that the computing power of a single data center is limited is broken through. Through unified modeling and scheduling of calculation, memory and network resources, task loads can be intelligently allocated according to hardware performance and network bandwidth of different data centers, and efficient collaborative utilization of computing power resources is realized. The training task of the super-large-scale model can be rapidly completed in the heterogeneous computing power environment, and the training time is remarkably shortened. The provided flexible parallelism degree allocation method can be adaptive to different task and resource conditions, the proportion of data parallelism, model parallelism and pipeline parallelism is automatically adjusted, the parallelism efficiency is improved, and the communication overhead is reduced. A training time estimation function is integrated, the overall time delay and resource requirements can be predicted before task execution, and a basis is provided for scheduling decision making.

This invention discloses a parallel optimization system for massive video processing. The system adopts a four-layer integrated parallel and collaborative processing architecture, comprising, from top to bottom: a parallel task layer for video stream access, grouping, splitting, encapsulation, and queue management; a resource abstraction layer for unified hardware modeling, status acquisition, topology construction, and capability assessment; a parallel scheduling layer for task-hardware matching, load balancing, priority scheduling, and dynamic adjustment; and an execution optimization layer for data stream localization, parallel read / write, cache optimization, and zero-copy processing. The parallel task layer, resource abstraction layer, parallel scheduling layer, and execution optimization layer form a complete parallel processing link: task input, resource awareness, accurate scheduling, and optimized execution. This invention implements concurrent rate limiting and smooth access for the input video stream to prevent traffic surges; and sets synchronization points and timing control for parallel tasks to ensure orderly output.

The application discloses a self-adaptive balanced division method based on GPU acceleration sparse-dense matrix multiplication, and comprises the following steps: analyzing a sparse matrix, determining long rows affecting parallel performance; dividing the long rows into equal "parts"; storing the divided sparse matrix by using a new storage format; loading all nonzero elements in the "parts" to a shared memory on a GPU; consuming the nonzero elements in the shared memory and multiplying corresponding elements of a dense matrix; adding the parts from the same row and obtaining a final result. The application aims at the current situation that long rows lead to low parallel efficiency when a row division mechanism is used in GPU acceleration sparse-dense multiplication, and proposes a self-adaptive balanced division method based on the structure characteristics of a GPU. The "parts" are used to replace rows as parallel granularity, and the size of the "parts" is controlled within a reasonable range to ensure that a thread group has enough threads to effectively parallelize the nonzero element task, and the similar size of the "parts" avoids the load imbalance among the thread groups.

The invention provides an automatic testing method and device based on test sequence generation, equipment and a medium, and relates to the technical field of server testing. The method comprises the following steps: acquiring natural language test requirement data, and generating a structured target test step sequence based on a test requirement; then resource state information of the environment to be tested is collected, the resource state information is combined with the target test step sequence, and a test task scheduling instruction used for indicating a step execution strategy is generated; and distributing the test task scheduling instruction to a plurality of distributed execution nodes in a to-be-tested environment, and executing test steps in the scheduling instruction by the distributed execution nodes to obtain a corresponding test execution result. According to the scheme, automatic generation from natural language requirements to executable test steps can be achieved, reasonable scheduling is carried out based on the environment resource condition, and the execution efficiency and accuracy of the test task in the distributed environment are improved.

The invention provides a neutron transport scanning operator optimization method based on built-in function and instruction level parallelism, and the method comprises the steps: firstly reconstructing a data layout, declaring an array according to an energy group sequence, carrying out the memory alignment, and enabling a calculation process to adapt to an SIMD vectorization architecture; then implementing explicit vectorization calculation by adopting a built-in function, performing polar angle cycle expansion and instruction recombination, and fully mining instruction-level parallel potential; meanwhile, key index calculation is optimized into vectoring polynomial approximation. Based on the optimized data flow and the parallel computing mode, efficient updating of the angular flux and the standard flux is achieved, and convergence judgment and calculation are completed. According to the method, the calculation throughput rate and the hardware resource utilization rate of the scanning operator are remarkably improved, and the method can be coordinated with coarse-grained parallel strategies such as MPI / OpenMP and is suitable for a multi-architecture high-performance calculation environment.

This invention discloses a method for parallelizing and pipelining a nested multiplier, relating to the field of intelligent warehousing technology. Based on the nested multiplication concept, the multiplication operation is decomposed into a formula to obtain the squaring operation of the high-bit part and the difference of squares plus shift operation of the low-bit part. Based on the characteristic of 2ab in the multiplication formula, the intermediate values ​​required for high-bit calculation are obtained by querying a preset low-bit square value table through the low-bit results. For batch data, multiple sets of data are processed simultaneously through a parallel architecture. The overall calculation process is divided into multiple pipeline stages, and continuous calculation is achieved through stage cascading. The pipeline output results of each parallel computing unit are collected, verified, and integrated to output a complete set of multiplication results. This invention achieves breakthroughs in hardware resources, computational latency, and batch throughput through the collaborative design of nested recursive simplification, pipeline reuse, and parallel architecture, providing an efficient solution for high real-time and high-parallelism digital computing scenarios.

The invention discloses a computing power resource dynamic scheduling system supporting trusted data exchange. The computing power resource dynamic scheduling system comprises an underlying hardware adaptation layer, a trusted data exchange layer, a core computing power optimization layer, a dynamic scheduling layer and a monitoring and feedback layer, wherein the bottom hardware adaptation layer comprises a chip migration adaptation module and is used for realizing instruction set mapping and capability portraying of heterogeneous hardware; the core computing power optimization layer comprises a low-delay reasoning system, an efficient N-dimensional parallel system and a heterogeneous memory management system; and the dynamic scheduling layer outputs a computing power distribution strategy based on the capability portrait and the task characteristics. According to the scheme, through deep fusion of hardware adaptation, credibility guarantee, computing power optimization and intelligent scheduling, a full-stack computing power scheduling system in a credible scene can be constructed, and the scheduling efficiency is improved.

This application discloses a generative semantic communication system for 3D content generation, comprising: a transmitter deployed on an edge device, a receiver deployed on a cloud server, and a wireless channel connecting the transmitter and receiver; the transmitter extracts visual semantic tokens from a single input 2D image to form a visual semantic token sequence; the visual semantic token sequence and the signal-to-noise ratio of the current wireless channel are used as input and mapped to a channel input symbol sequence for transmission; the receiver recovers the semantic token sequence from the received signal; and a 3D mesh model is generated based on the recovered semantic token sequence; thereby, by transmitting compact visual semantic tokens instead of raw data, the wireless bandwidth requirement is significantly reduced; an efficient adaptive transmission architecture based on structured state space duality is adopted, which improves parallel efficiency while maintaining linear computational complexity, and integrates a channel adaptive state adjustment module to dynamically adapt to time-varying channels.

The invention belongs to the technical field of large language models, and particularly relates to a large language model KV Cache unloading optimization method. Comprising the following steps: inputting a plurality of marks obtained by performing word segmentation processing on a to-be-processed text into a large language model; aiming at the current mark of the current attention layer, pre-selecting a key KV index set of the next mark of the current attention layer by using a cross-mark pre-selection mechanism; loading the key KV of the current mark in the next attention layer pre-selected by the previous mark by using a cross-mark pre-selection mechanism to the GPU from the external storage; the GPU adopts a KV cache adaptive hierarchical management strategy to manage the cache; the GPU executes sparse reasoning calculation which is currently marked on the current attention layer; taking the next attention layer as the current attention layer, and repeating the reasoning process until a final reasoning result of the large language model is output; according to the method, the transmission bottleneck caused by interlayer heterogeneity is relieved fundamentally, and low-delay and high-throughput large language model reasoning is realized.

The application belongs to the technical field of offshore target drift tracking, and specifically discloses a multi-core parallel particle tracking acceleration method for large-range marine drifting targets. First, an offshore target drift prediction model is constructed; a forecast area satellite remote sensing image is acquired to obtain an initial distribution position of the offshore target; model calculation area, particle number and prediction time length model parameters are set; model driving fields such as wind field and flow field are acquired; parallel setting is performed on a multi-core processor, including the number of calculation CPUs and the number of physical cores, the number of running threads, task division, one-time thread pool creation and scheduling strategy setting; particle state is initialized, a time advancement and drift numerical simulation process is performed, large-scale drift particles are tracked and calculated in parallel, and finally a particle trajectory set is predicted. The method realizes high-fidelity and fine drift prediction within a minute-level time limit.