Video decoding macro-block-grade parallel scheduling method for perceiving calculation complexity

A technology of computational complexity and scheduling method, applied in the direction of digital video signal modification, image communication, electrical components, etc., can solve the problem of incompatibility and inability to make full use of GPU stream processors, to improve parallel efficiency, reduce synchronization overhead, The effect of efficient parallel decoding

Inactive Publication Date: 2016-04-13
HUAZHONG UNIV OF SCI & TECH
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Problems solved by technology

Because the number of CPU cores is relatively small, the number of parallel threads is limited, and the existing ordinary GPU generally has thousands of stream processors. The number of threads in the CPU-based scheduling scheme is kept at the same level as the number of CPU cores. Quantitative level, so can not take full advantage of the many stream processors that the GPU has
In addition, the parallel scheduling scheme implemented by queues and thread pools requires a lot of logical judgments, and GPU is more suitable for arithmetic operations, not suitable for this type of scheduling

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  • Video decoding macro-block-grade parallel scheduling method for perceiving calculation complexity
  • Video decoding macro-block-grade parallel scheduling method for perceiving calculation complexity
  • Video decoding macro-block-grade parallel scheduling method for perceiving calculation complexity

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[0038] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not constitute a conflict with each other.

[0039] System structure diagram of the present invention sees attached figure 2 , where the entire decoding process is divided into three major stages, CPU computing module, scheduling module, and GPU parallel computing module. The CPU calculation module includes two calculation stages of entropy decoding and reordering. The scheduling module includes complexity estimation modeling and calcula...

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Abstract

The invention discloses a video decoding macro-block-grade parallel scheduling method for perceiving calculation complexity. The method comprises two critical technologies: the first one involves establishing a macro-block decoding complexity prediction linear model according to entropy decoding and macro-block information after reordering such as the number of non-zero coefficients, macro-block interframe predictive coding types, motion vectors and the like, performing complexity analysis on each module, and fully utilizing known macro-block information so as to improve the parallel efficiency; and the second one involves combining macro-block decoding complexity with calculation parallel under the condition that macro-block decoding dependence is satisfied, performing packet parallel execution on macro-blocks according to an ordering result, dynamically determining the packet size according to the calculation capability of a GPU, and dynamically determining the packet number according to the number of macro-blocks which are currently parallel so that the emission frequency of core functions is also controlled while full utilization of the GPU is guaranteed and high-efficiency parallel is realized. Besides, parallel cooperative operation of a CPU and the GPU is realized by use of a buffer area mode, resources are fully utilized, and idle waiting is reduced.

Description

technical field [0001] The present invention belongs to the technical field of video decoding, and more specifically relates to a computational complexity-aware macroblock-level parallel scheduling method for video decoding. The estimation result of stage computational complexity schedules the parallel execution sequence of macroblock decoding in the video frame, reduces the synchronization overhead of parallel processing, achieves the effect of accelerating video decoding and saving system energy consumption. Background technique [0002] At present, in applications such as digital TV, mobile video, and video surveillance, full high-definition 1080P digital video has become very popular, and video resolution is developing toward ultra-high-definition, such as 4K and 8K. The improvement of video resolution can provide a better user experience, but it also increases the computational complexity of the encoding and decoding process dramatically, posing a huge challenge to its ...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04N19/13H04N19/176H04N19/42H04N19/61H04N19/86
Inventor 郭红星潘俊夫朱文周
Owner HUAZHONG UNIV OF SCI & TECH
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