Multi-core processor synchronization method based on delay fence synchronization operation instruction

A technology of multi-core processors and core processors, applied in the direction of concurrent instruction execution, electrical digital data processing, instruments, etc., can solve the problems of cost, physical distance, etc., and achieve the goal of reducing synchronization overhead, improving efficiency, and reducing barrier synchronization operations Effect
CN110147253AActive Publication Date: 2019-08-20NAT UNIV OF DEFENSE TECH
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Patent Information

Authority / Receiving Office
CN Β· China
Patent Type
Applications(China)
Current Assignee / Owner
NAT UNIV OF DEFENSE TECH
Publication Date
2019-08-20

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Abstract

The invention discloses a multi-core processor synchronization method based on a delay fence synchronization operation instruction, and the method comprises the steps: enabling all participating coreprocessors to send out a synchronization arrival signal of the core processor at a synchronization arrival station, and confirming whether other core processors participating in the fence synchronization all arrive at a synchronization inspection station; and if yes, enabling the core processor to continue to execute, otherwise, enabling the core processor to enter a waiting state until the last arrived signal sent by the core processor is checked by the core processor. The synchronous arrival station is a pipeline station where the synchronous arrival station is located in a self-synchronousstate updating mode; the synchronous check station is a pipeline station where the synchronous state of other cores is inquired, and when the synchronous check station and the synchronous arrival station are not the same pipeline station, the non-adjacent synchronization mode is delay synchronization. The method has the advantages that the method is realized based on any instruction type, extra fence synchronization operation can be reduced, and the transaction synchronization efficiency is improved.
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Description

technical field

[0001] The invention mainly relates to the field of microprocessors, in particular to a multi-core processor synchronization method with a delay fence synchronization operation instruction. Background technique

[0002] In modern processors, an instruction usually needs to go through multiple pipeline stations from acquisition to execution, such as instruction address generation, instruction memory access, instruction issuance, decoding, and multiple (1-N) execution stations.

[0003] Fence synchronization is an operation often involved in multi-core processing, which guarantees the order of transaction processing between multiple cores. The implementation of fence synchronization uses Load / Store type instructions to operate memory or memory-mapped registers. For example, some processors provide atomic operation instructions, and these atomic operation instructions operate on memory to construct fence synchronization operations; there are also some processors...

Claims

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